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1. 发明专利

JPH01311340A MULTI-DIMENSIONAL ADDRESS FORMING CIRCUIT FOR MULTI-BANK MEMORY 失效
公开(公告)号：JPH01311340A
公开(公告)日：1989-12-15
申请号：JP14306688
申请日：1988-06-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MINAMI TOSHIHIRO , TASHIRO YUTAKA , YAMAUCHI HIROKI , HAMAGUCHI SHIGETAKE , TSUCHIYA TOSHIO
IPC分类号： G06F12/02 , G06F12/06
摘要： PURPOSE:To simplify the control of an address forming circuit by providing the title circuit with a storage part for displacement to be an one-dimensional intra-bank address and a shifter for moving an individual displacement correspondingly to a chane in a bank number. CONSTITUTION:A reference address forming circuit 1 forms the intra-bank address and bank number of reference data and the bank number is compared with the bank numbers of individual banks by comparators 40-414 corresponding to respective banks. Selectors 50-514 are controlled so that '0' is selected when the bank number of the reference data is smaller than the bank numbers of individual banks or '1' is selected when larger than them. Displacement values stored in a register group 2 to be the storage parts of the displacement values are shifted by the same number of words as each bank number through respective word terminals of a barrel shifter 3. The shifted results are added by 3- input address 60-615, latched by registers 70-715 and read out from bank-divided memories 80-815 in parallel.

2. 发明专利

JPH0360181B2 失效
公开(公告)号：JPH0360181B2
公开(公告)日：1991-09-12
申请号：JP10477584
申请日：1984-05-25
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KONDO TOSHIO , HAMAGUCHI SHIGETAKE , TSUCHA TOSHIO , NAKAJIMA TAKATOSHI
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/118

3. 发明专利

JPS63223990A CONNECTION TEST SYSTEM 失效
公开(公告)号：JPS63223990A
公开(公告)日：1988-09-19
申请号：JP5843887
申请日：1987-03-13
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HAMAGUCHI SHIGETAKE
IPC分类号： G06K9/72 , G10L11/00 , G10L15/10 , G10L15/18 , G10L15/28
摘要： PURPOSE:To obtain a practical connection testing method for voice and characters which is short in response time by checking whether or not unit pieces of information which adjoin each other in an information sequence have specific connection relation as to respective information sequences and thus taking a connection test. CONSTITUTION:The processing for the connection test consists of 1st-5th stages. In the 5th stage, the number of times of the reading of a memory circuit M1 is K . In this case, K is the number of candidates for respective units of information of information A to be inspected. The numbers of times of the reading of memory circuits M2-Mj-1. Therefore, the processing needs to be performed [K +CXK(J-2)] time in the 5th stage. Here, J is represents the length of a unit information sequence A. The connection test processing needs to be performed as many times as shown by an equation I in the 2nd-5th stages in total except the 1st stage. The processing time of one time is 100-500msec and the total time is 0.5-2.7msec, so the processing is speeded up by >=2 digits as compared with a 270msec processing time.

4. 发明专利

JPS53109481A TEST METHOD FOR SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPS53109481A
公开(公告)日：1978-09-25
申请号：JP2387777
申请日：1977-03-07
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HAMAGUCHI SHIGETAKE , ISHIKAWA KOUJI
IPC分类号： G01R31/26 , G01R31/28 , G01R31/30
摘要： PURPOSE:To efficiently analyse the operating performance, by providing the means forming the test pulse based on the power supply and the clock voltage at operation and non-operation area of the semiconductor circuit and the means changing the delay time and pulse width through the application of the pulse to the circuit, and by detecting the part of circuit defective with this result.

5. 发明专利

JPS5382237A TEST PATTERN OF SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPS5382237A
公开(公告)日：1978-07-20
申请号：JP15757076
申请日：1976-12-28
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NARUMI NAOAKI , HAMAGUCHI SHIGETAKE , ISHIKAWA KOUJI , OOGUCHI OSAMU
IPC分类号： G11C11/413 , G01R31/26 , G01R31/28 , G01R31/3183 , G06F11/00 , G06F11/22 , G11C11/34 , G11C29/10
摘要： PURPOSE:To analyse test results efficiently by performing operation confirmation in a transistor unit of minimum units which constitute a tested circuit and making the relation to circuit operation close.

6. 发明专利

JPH01310445A PARALLEL ARITHMETIC PROCESSOR 失效
公开(公告)号：JPH01310445A
公开(公告)日：1989-12-14
申请号：JP14089488
申请日：1988-06-08
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TASHIRO YUTAKA , MINAMI TOSHIHIRO , TSUCHIYA TOSHIO , HAMAGUCHI SHIGETAKE , YAMAUCHI HIROKI , SUZUKI YUTAKA , KURODA HIDEO
IPC分类号： G06F9/38 , G06F15/16
摘要： PURPOSE:To improve the processing speed of repeating operation by executing repeatedly an operation based on a command until a computing element Pi itself satisfies the scheduled setting conditions for a command outputted from a command preparing circuit in the computing element Pi. CONSTITUTION:A scheduled command is outputted from a command preparing circuit 2 to all computing elements P1-Pn and thus, all computing elements P1-Pn simultaneously start the same operation based on a command C from the command preparing circuit 2. A computing element P repeatedly executes the operation base on the command C until the computing element Pi itself satisfies the scheduled setting conditions. When the computing element Pi satisfies the scheduled setting conditions, a flag Fi to show it is hoisted, and stored into a (made into 1) flag memory Mi. Simultaneously, a gate closing signal is sent to a gate circuit Gi to stop the supply of the clock pulse to a computing element Pi; thereby stopping the operation of and computing element Pi.

7. 发明专利

JPS60250661A ARRAY CIRCUIT IN INTEGRATED CIRCUIT CHIP 失效
公开(公告)号：JPS60250661A
公开(公告)日：1985-12-11
申请号：JP10477584
申请日：1984-05-25
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KONDOU TOSHIO , HAMAGUCHI SHIGETAKE , TSUCHIYA TOSHIO , NAKAJIMA TAKATOSHI
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/118
摘要： PURPOSE:To reduce the occupying area while maintaining simple wirings and shortage by removing the shape of a circuit unit from a square but approaching as a whole to the square to align the row (column) of the circuit units at every other one at right and left side (at upper and lower sides) in two rows (columns). CONSTITUTION:Circuit units 1 are formed in a longitudinally long length, and arranged in two rows sorted at A11-A41 at left side from below, at B11-B41 at right side, at A12-A42 at left side, at B12-B42 at right side. According to this configuration, the shape of the unit 1 is formed in a longitudinally long length, but approached to square by combination array of rows A and B. In this array, wirings of data transfer connecting wirings 2 are complexed to be thought to increase the occupying area. However, a multilayer wiring structure is employed through data transfer connecting wirings 2 and common signal wirings 3 on the circuit units, and when the wiring layers are suitably used, if the common signal wirings are many, considerable occupying area can be reduced to provide simple wirings and shortage maintained in the same manner as the conventional array.

8. 发明专利

JPS53138648A TEST PATTERN FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS53138648A
公开(公告)日：1978-12-04
申请号：JP5337977
申请日：1977-05-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HAMAGUCHI SHIGETAKE , ISHIKAWA KOUJI
IPC分类号： G01R31/28 , G01R31/26 , G01R31/30 , G01R31/3183
摘要： PURPOSE:To ensure an assured analysis for the limit decision factor of the active margin by carrying out a test through combinations of plural test conditions at the active region, the inactive region or the intermediate region while supplying the input information pattern row to the tested device.

9. 发明专利

JPH01311341A MODULO ADDRESS FORMING CIRCUIT FOR MULTI-BANK MEMORY 失效
公开(公告)号：JPH01311341A
公开(公告)日：1989-12-15
申请号：JP14306788
申请日：1988-06-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MINAMI TOSHIHIRO , TASHIRO YUTAKA , YAMAUCHI HIROKI , HAMAGUCHI SHIGETAKE , TSUCHIYA TOSHIO
IPC分类号： G06F12/02 , G06F12/06
摘要： PURPOSE:To simplify the control of an address forming circuit by adding the intra-bank address of reference data to values changed by the outputs of respective comparators and masking the upper bit of the outputted intra-bank address. CONSTITUTION:A reference address forming circuit 1 calculates the intra-bank address and bank number of reference data and the bank number is compared with the bank numbers of individual banks by comparators 60-614 corresponding to respective banks. Selectors 70-714 are controlled so that '0' is selected when the bank number of the reference data is less than the bank numbers of individual banks or '1' is selected when larger than them. Then, '0' or '1' is respectively added by address 80-814. Values obtained by substituting '0' for the upper bits from the n-th bit counted from the LSB side of respective values of the banks 0-14 by mask circuits 90-914 are added to a base address BA in a base address storage part 10 by adders 110-1115. The outputs of the adders 110-1115 are latched by registers 120-1215 and read out from memories 130-1315 in parallel.

10. 发明专利

JPH01311339A PARALLEL ADDRESS FORMING CIRCUIT FOR MULTI-BANK MEMORY 失效
公开(公告)号：JPH01311339A
公开(公告)日：1989-12-15
申请号：JP14306588
申请日：1988-06-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MINAMI TOSHIHIRO , TASHIRO YUTAKA , YAMAUCHI HIROKI , HAMAGUCHI SHIGETAKE , TSUCHIYA TOSHIO
IPC分类号： G06F12/02 , G06F12/06
摘要： PURPOSE:To simplify an address forming circuit by detecting the size relation between the bank number of data to be read and that of reference data and changing addition based upon the detected output. CONSTITUTION:A reference address forming circuit 1 forms the intra-bank address and bank number of reference data and the bank number is compared with the bank numbers of individual banks by comparators 20-214 corresponding to respective banks. Selectors 30-314 are controlled so that '0' is selected when the bank number of the reference data is smaller than the bank numbers of individual banks. The selectors 30-314 are also controlled so that '1' is selected when the number of the reference data is larger than the bank numbers of individual banks and '1' is added by adders 40-414. The added results are latched by registers 50-515 and read out from bank-divided memories 60-615 in parallel. Consequently, the address forming circuit can be simplified without forming complex address forming circuits corresponding to individual banks.

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