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1. 发明专利

JPS5537007A OBSTACLE MONITORING CONCENTRATION MANAGEMENT SYSTEM 失效
公开(公告)号：JPS5537007A
公开(公告)日：1980-03-14
申请号：JP10956778
申请日：1978-09-08
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： OKAJIMA KEISUKE , KAWASAKI TAKESHI , TAKAHASHI HIDEO , YAMASHITA YOSHIO , AWAJI TOSHIO
IPC分类号： H04M3/08 , H04M3/22 , H04Q3/545
摘要： PURPOSE:To carry out the rapid and precise detection of the obstacle by concentration monitoring flip flop for informing the obstacle correspondingly provided to the respective communication passage device and the communication passage device control processor. CONSTITUTION:When the failure is generated in the communication passage device 11, 12..., and the communication passage device control processor 71, 72..., the indication of the respective failure or obstacle causes is given to the failure communicating flip flop 21, 22... OR of a plurality indication bits of the respective failure causes corresponding to the respective FF21... is taken out by OR circuit 51, 52... and the output thereof is pulled into the failure concentration management FF60, thereby the concentration and the gradation of the monitor point are performed and the monitoring of the communication passage system can be done only by the monitor of FF60. The monitoring is done by one processor of the exchange processor groups.

2. 发明专利

JPS5531322A RISING SYSTEM FOR SYSTEM 失效
公开(公告)号：JPS5531322A
公开(公告)日：1980-03-05
申请号：JP10445478
申请日：1978-08-29
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MORITA SHIGEO , KAWASAKI TAKESHI , KATOU HIROYUKI , OKAJIMA KEISUKE , SEIKE KENJI
IPC分类号： G06F9/445 , G06F15/16 , G06F15/177 , H04Q3/545
摘要： PURPOSE:To give a quick and well-ordered rising to the electronic exchange system of multi-processor system without causing any confusion as a system by giving the wake-up to the processors and memories in sequence based on the specified processor among the central processors. CONSTITUTION:At the opening time of the station, all programs, data and the like which are used within the system are transferred from the file memory (FM) to the bubble memory (MB) under the control of MCP(CPN+1, CPN+2) which is a specified processor. Then the MCP starts the fault process circuit (FPC). The FPC gives a command to the MCP to transfer the system rising program to the local memory (IM) of the MCP from the MB. After this, the MCP makes the program within the IM run to transfer the program and the data to be supplied to the IM of each CP from the MB to the common memory (CM). Furthermore, the MCP starts the mu-program of each CP and then makes each CP transfer the infromation within CM to the IM of its own. The MCP has the same behavior also to the peripheral control unit NP.

3. 发明专利

JPS55150200A CHECK SYSTEM FOR MEMORY DESTRUCTION 失效
公开(公告)号：JPS55150200A
公开(公告)日：1980-11-21
申请号：JP5730079
申请日：1979-05-10
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： KOIZUMI TADASHI , SUYAMA MASATO , MANABE SHIROU , OKAJIMA KEISUKE , ENDOU KAZUMI
IPC分类号： G06F12/16 , G11C29/00
摘要： PURPOSE:To obtain a memory destruction check system of simple constitution which simplifies measures against software bugs by generating redundant information corresponding to a random part of a memory and then by checking whether the part is destroyed. CONSTITUTION:When an instruction consisting of function code (f) for redundant information generation, and operands 1 and 2 assigning address (a) and word length (n) is decoded, the address and redundant information are stored in registers WR1 and WR4 by way of work registers WR1-WR4 and an arithmetic circuit connected to bus. When code (f) shows an end instruction for the memory check by redundant information, the redundant information is similarly stored in data buffer DB according to the address of register WR1 and then compared to the contents of register WR4, thereby checking whether a random part in memory is destroyed by using the redundant information. Therefore, a system of simple constitution is realized which eliminates the need for time division and simplifies measures against software bugs.

4. 发明专利

JPS5544234A FIXED PATTERN DELIVERY SYSTEM 失效
公开(公告)号：JPS5544234A
公开(公告)日：1980-03-28
申请号：JP11668078
申请日：1978-09-25
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： NARA EIZOU , HAMASATO KAZUO , HIGAKE MASAKATSU , OKAJIMA KEISUKE , AWAJI TOSHIO
IPC分类号： H04M19/00 , H04M19/02 , H04Q11/04
摘要： PURPOSE:To enable non-block distribution corresponding to the call for the call tone, busy tone and talkie, by locating the PCM code of one sound source on highway scattering in timingwise, in the time sharing communication path. CONSTITUTION:The same PCM code fixed pattern TK corresponding to signal or talkie is located to the highway for test HWt in scattering by timingwise, and depending on the content of the communication control memory SCM, it is written in the address corresponding to the primary switch PSW of the digital communication path subunit SUO. The data written in the primary switch PSW is fixedly exchanged at the time sharing junctor TDJ and delivered to the secondary switch SSW in distribution. When the call requiring the signal delivery corresponding to the fixed pattern TK is produced on the highway HWn, the fixed pattern is delivered from the secondary switch PSW with the communication path control memory SCM.

5. 发明专利

JPS5537626A LOAD DECENTRALIZATION SYSTEM 失效
公开(公告)号：JPS5537626A
公开(公告)日：1980-03-15
申请号：JP10956578
申请日：1978-09-08
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OKAJIMA KEISUKE , KIN KATSUYOSHI
IPC分类号： G06F15/16 , G05D3/12 , G06F15/00 , G06F15/177
摘要： PURPOSE:To decentralize loads evenly by allowing a job schedule processor to register a request of a job to be executed to a queue on a common memory and each processor to receive and execute this job request. CONSTITUTION:Assigned job schedule processor PC210 links at a certain point in time a job request to be executed to job request queue 310 on common memory 300. Other PCs 220 and 230 fetch and execute sequentially jobs from queue 310 and then move to next job requests. On finishing a scheduled job, PC 210 also fetches and executes a job request from queue 310 as well as other PCs 220 and 230. In this way, after each job is finished, each PC fetches a next job request at random, so that loads will be decentralized on the whole.

6. 发明专利

JPS57209558A EMERGENCY INFORMATION SYSTEM BETWEEN PROCESSORS 失效
公开(公告)号：JPS57209558A
公开(公告)日：1982-12-22
申请号：JP9385381
申请日：1981-06-19
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OKAJIMA KEISUKE , KUSABA AKIRA , SHINPO ISAO
IPC分类号： G06F15/16 , G06F11/00 , G06F15/177
摘要： PURPOSE:To simplify the processing steps through the improvement of the reliability and processing capability of a system, by providing an emergency information means processors and an instruction to control the means for the processors among. CONSTITUTION:An instruction consists of a processor designation section and an emergency instructing section, a processor designation section of the instructions stored in buffer registers 2011, 3011 and 4011 is interpreted with instruction decoders 2012, 3012 and 4012, and drives emergency instruction gates 2013, 3013 and 4013 when all processors or the processor concerned is designated, and transfers the information in the mergency instruction section to emergency instruction display registers 2014, 3014 and 4014. When the information of the emergency instruction section is written in the registers 2014, 3014 and 4014, interruption control circuits 202, 302 and 402 are started with interruption gates 2015, 3015 and 4015 to cause interruption. Central controllers 204, 304 and 404 for the processors 200, 300 and 400 read the content of the registers 2014, 3014 and 4014 via processor buses 203, 303 and 403.

7. 发明专利

JPH05122383A COMMON LINE COMMUNICATION CONTROL SYSTEM 失效
公开(公告)号：JPH05122383A
公开(公告)日：1993-05-18
申请号：JP27576091
申请日：1991-10-23
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： MATSUNAGA FUTOSHI , OKAJIMA KEISUKE , ABEKAWA HITOSHI
IPC分类号： H04M3/00 , H04M7/06
摘要： PURPOSE:To attain common communication control between exchanges smoothly with a high efficiency by sending the state of a relevant exchange to a sender side exchange when the reception of the information sent from other exchange is rejected. CONSTITUTION:For example, a common line signal processing unit 2b receives transmission information from a sender side exchange 1a, priority is identified from the transmission information. Then the propriety of reception is discriminated based on the state of an exchange 1b registered in an exchange state identification memory 6b and the identified priority. In the case of rejecting the reception as the result, the state of the exchange 1b (such as in congestion or in failure) is returned to the sender exchange 1a. Thus, the sender side exchange 1a takes procedure with respect to the reception rejection and the receiver side exchange 1b does not make reception processing but rejects the reception and implements smooth and highly efficient common line communication.

8. 发明专利

JPH0397332A INTER-PROCESSOR COMMUNICATION METHOD 失效
公开(公告)号：JPH0397332A
公开(公告)日：1991-04-23
申请号：JP23278289
申请日：1989-09-11
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE , KUSABA KEIZO
IPC分类号： G06F15/16 , G06F15/163 , G06F15/177
摘要： PURPOSE:To expand an inter-processor maximum communication capacity by allowing the cell decomposing device of a transmission processor to divide communication information into cells, sending them to a reception processor via an ATM speech path and composing the received cells with a cell assembling device to generate communication information. CONSTITUTION:A processor 110 writes the information desired of communication into a memory 120. A reception module 300 receives a cell with a buffer register 330 and sends information attribute display in a header to decoders 360, 310. A decoder 362 receives a transmission module number from a message register 330 and selects a cell assembling device corresponding to the module number. A memory write register 376 writes inter-processor communication information to the memory 320 according to the reception buffer address to realize simultaneous inter-processor communication from plural transmission modules.

9. 发明专利

JPH02123850A INTER-PROCESSOR COMMUNICATION METHOD 失效
公开(公告)号：JPH02123850A
公开(公告)日：1990-05-11
申请号：JP27624188
申请日：1988-11-02
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To eliminate the need for an exclusive inter-processor communication equipment by providing an identification field for transfer information sent in a form of end-end and inter-processor communication information required for the exchange processing after the setting of a call to the transfer information in a cell passing through an in-channel and referencing the field so as to extract the inter-processor communication information from a channel. CONSTITUTION:A cell passing through an in-channel in a decentralized control type ATM(Asynchronous Transfer Mode) exchange, and an identification field for the transfer information sent in a form of end-end and the inter-processor communication information required for the exchange processing after the setting of a call in the received cell is referenced to extract the inter-processor communication information from a channel. Moreover, a field identifying a signal type a call processing signal for the inter-processor communication information, a maintenance operation signal and a fault processing signal or the like is referenced to supply the inter-processor communication information to a program of each function. Thus, the inter-processor communication not requiring an exclusive inter-processor communication equipment is realized to reduce the hardware cost.

10. 发明专利

JPH0387962A INTER-PROCESSOR COMMUNICATION CONTROL METHOD 失效
公开(公告)号：JPH0387962A
公开(公告)日：1991-04-12
申请号：JP23158889
申请日：1989-09-08
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE , MATSUNAGA FUTOSHI , KUSABA KEIZO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To attain the smooth and highly efficient communication between processors by deciding autonomously the propriety of receiving the communication information from other processors based on the processor state, i.e., the contents of a register and informing a transmission processor of the reason for rejection of receiving the communication information if decided to 'No'. CONSTITUTION:A register 206 (406) which stores the state of a processor 10 (30) contained in an inter-processor communication equipment 20 (40) grasps the normal state, the congestion state, the initialization state, the faulty state, etc., of the reception processor 30 (10) based on the contents of the register 206 (406) in the reception mode of the equipment 20 (40) to decide the propriety of reception. Thus the propriety of reception is decided in accordance with the degree of congestion and the priority of the communication information if the processor 10 (30) is kept in a congestion state. When the rejection of receiving the information is decided, the equipment 20 (40) informs the transmission processor 10 (30) of the reason for rejection. Thus the processor 10 (30) can decide the propriety and the necessity for retransmission of the information based on the received reason. Meanwhile the processor 30 (10) can reject the reception of the information without performing any reception process. Thus the smooth and highly efficient communication is attained between both processors.

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