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1. 发明专利

JPH0318970A JAPANESE SENTENCE INTERFACE GENERATING DEVICE 失效
公开(公告)号：JPH0318970A
公开(公告)日：1991-01-28
申请号：JP15433489
申请日：1989-06-15
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO
IPC分类号： G06F17/21
摘要： PURPOSE:To enable anyone to construct a compact Japanese sentence interface by registering the grammars and vocabularies via a register/editor device and analyzing the structure of the Japanese sentence inputted via a sentence structure analyzing device set previously. CONSTITUTION:A register/editor device 101 to register the contents of a grammar dictionary, a vocabulary dictionary, and a generation description dictionary, a Japaneseword input part 102 which inputs the Japanese sentences by reference to a registered vocabulary dictionary, a sentence structure analyzing device 103 which analyzes the sentence structures with the Japanese sentences used as inputs, a generating device 104 which inputs the analyzing result of the sentence structure and produces an instruction sentence to be given to a computer are provided. Then a dictionary necessary for analysis of the Japanese sentence for a Japanese sentence interface is registered via the device 101. Thus even a user having no technical knowledge can register grammars. Then the registered grammar can analyze the input Japanese sentence without deteriorating the flexibility of the Japanese language nor giving the special limitation to the users. In addition, the dictionary capacity is extremely reduced since only the necessary grammars and vocabularies are registered via the device 101.

2. 发明专利

JPH01269344A DATA TRANSMISSION AND RECEPTION SYSTEM 失效
公开(公告)号：JPH01269344A
公开(公告)日：1989-10-26
申请号：JP9870388
申请日：1988-04-20
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO
IPC分类号： H04L27/18 , G06K17/00 , H04B5/00 , H04L25/02 , H04L25/49
摘要： PURPOSE:To reduce a consumption current and an element scale on a reception side by providing a transmission means transmitting data, power and a carrier and a reception means transmitting holding data to the transmission means, and transmitting data from the reception means to the transmission means by a PSK system. CONSTITUTION:A certain oscillation waveform in a high frequency is outputted from an oscillation circuit 1, is turned into a carrier frequency and is conveyed from a transmission coil A5 on a transmission side to a reception coil B7 on the reception side. A signal conveyed to the reception coil B7 is furthermore turned into the input of a frequency-dividing circuit A9. Thus, the same waveform can be obtained for the outputs of the frequency-dividing circuits A9 and B2. The frequency-dividing circuit A9 generates a PSK signal from a data input from a data input terminal 14 in a control circuit A11, and the signal is transmitted to a reception coil A6 on the transmission side through a transmission coil B13 on the reception side, whereby it is adjusted to a power level through a waveform shaping circuit 3. A comparison circuit 4 compares the output of the waveform shaping circuit 3 and the result can be obtained from a data output terminal 15.

3. 发明专利

JPH01268162A INTEGRATED CIRCUIT USING SCHOTTKY BARRIER DIODE 失效
公开(公告)号：JPH01268162A
公开(公告)日：1989-10-25
申请号：JP9744888
申请日：1988-04-20
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO
IPC分类号： H01L21/822 , H01L27/04 , H01L27/10 , H01L29/47 , H01L29/872 , H03K17/76
摘要： PURPOSE:To eliminate the cost of a component of a Schottky barrier diode, a space for placing the diode, labor of mounting the diode, etc. by inputting the diode in an integrated circuit, and incorporating a circuit for outputting a high potential signal of two input terminals in an integrated circuit. CONSTITUTION:A VDD power source 6, a backup power source 7, a VDD terminal 8, a backup power source terminal 9, a GND terminal 10, a first Schottky barrier diode 11, a second Schottky barrier diode 12, a RAM 13, an analog or logic circuit 14, and a switch 15 are provided. In this integrated circuit, a voltage of the terminal 9 or more is applied to the terminal 8 by the power source 6 when it is desired to be operated. When the operation is completed, the switch 15 is disconnected, the potential of the terminal 8 becomes the same as that of the terminal 10, and the power of the circuit 14 is not supplied. Accordingly, the integrated circuit is not operated. However, since the backup power for holding a memory is supplied through the diode 12 to the RAM 13 from the power source 7, the content of the RAM 13 is held.

4. 发明专利

JPS63169816A VOLTAGE COMPARATOR CIRCUIT 失效
公开(公告)号：JPS63169816A
公开(公告)日：1988-07-13
申请号：JP221387
申请日：1987-01-07
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO , SUGAWARA MITSUTOSHI
IPC分类号： H03K5/08 , G01R19/165 , H03K5/007 , H03K5/1252 , H03K5/24
摘要： PURPOSE:To surely decide the logic level of an input signal by providing a capacitor whose one end is connected to an input terminal and whose other end is connected to a 2nd input terminal of a voltage comparator and a voltage supply circuit approaching the voltage of the 2nd input terminal of the voltage comparator gradually to a reference voltage of a 1st input terminal so as to sense a steep current flowing to the capacitor. CONSTITUTION:Since a current flows from a power supply 7 to a diode 4 via a resistor 5, the reference voltage of a voltage comparator 8 is always kept higher than the ground potential by a forward voltage drop Vf1 of the diode 4. When the input signal S1 having an amplitude V is impressed to an input terminal 1, the potential S2 at a point A at a time t1 rises steeply based on the leading. When the input signal S1 descends at a time t2, the potential S2 at the point A is decreased by the voltage V and the voltage rises gradually till the next leading of the input signal S1 according to the time constant comprising a capacitor 2 and a resistor 6 and approaches the voltage Ff1 of the point B. Thus, the logic level of the input signal is decided surely independently of the potential change in the input signal or the change in the reference voltage of the voltage comparator.

5. 发明专利

JPH04138746A FREQUENCY DISCRIMINATION CIRCUIT 失效
公开(公告)号：JPH04138746A
公开(公告)日：1992-05-13
申请号：JP26112290
申请日：1990-09-29
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO
IPC分类号： H04L27/14 , H04L27/156
摘要： PURPOSE:To attain frequency discrimination within a wide frequency range by comparing charges stored in two capacitors at a comparator so as to discriminate the frequency. CONSTITUTION:While a reset pulse is inputted to a reset signal input terminal 2, an N-channel MOS transistor(TR) 11 is turned on and a switch 5 is turned off. That is, a noninverting input terminal of a comparator 10 goes to an L level. On the other hand, a switch 4 is closed by the reset pulse. Then a data clock signal A inputted to a data signal input terminal 1 in this case is inputted to a time constant circuit comprising a resistor 6 and a capacitor 7, and after the reset is released, the switch 4 is opened. Since the width of the reset pulse is equal to one cycle of a data clock signal A, the charge by one clock pulse is stored in the capacitor 7. Thus, an inverting input terminal of the comparator 10 goes to an H level and a noninverting input terminal goes to an L level for a block N1, then an output signal C of the comparator 10 goes to an L level and an output signal D of a binary flip-flop circuit 13 goes to an L level.

6. 发明专利

JPH0248817A FREQUENCY CONVERSION CIRCUIT 失效
公开(公告)号：JPH0248817A
公开(公告)日：1990-02-19
申请号：JP20048288
申请日：1988-08-10
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO
IPC分类号： H03K5/00
摘要： PURPOSE:To suppress the duty ratio near 50% and to multiply the frequency by 2 by forming an oscillation circuit having a frequency sufficiently larger than the frequency of an input signal on an LSI. CONSTITUTION:N sets of pulses are counted by a counter A5 when an input signal at an H level, the output of the counter A5 is supplied to a latch 8 at the fall of an input signal and a switch circuit 6 shifts the signal by one bit and latches the result. Then the input signal goes to an L level and the counter A5 is reset. When a counter B9 reaches N/2, the content of the latch 8 and the content of the counter B9 are coincident, the counter B9 is reset by a coincidence signal from a comparator circuit 10 and no coincidence signal is outputted. A pulse from the comparator circuit 10 is detected by a pulse detection circuit 11 and the output signal is inverted. Thus, the output signal is inverted at each N/2 of the oscillated pulse and the frequency is multiplied by 2 .

7. 发明专利

JPS63232708A FREQUENCY MULTIPLICATION CIRCUIT 失效
公开(公告)号：JPS63232708A
公开(公告)日：1988-09-28
申请号：JP6614087
申请日：1987-03-20
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO
IPC分类号： H03K5/00
摘要： PURPOSE:To prevent an influence due to the fluctuation of a parameter by forming an oscillation circuit which has a sufficiently larger frequency than the frequency of an input signal, and presuming the half of a period, during which the input signal is inputted, by using a counter and a 1/2 latch. CONSTITUTION:A CR oscillator 1 is designed beforehand so as to oscillate at the sufficiently larger frequency f2 than the frequency f1 of the input signal from a terminal 2, and when the input signal pulse is L, the output pulse of the oscillator 1 at the time when the input pulse is H is counted by the counter 5 which is reset through a delay circuit 6. Then, according to the signal of an invertor 7, the value of the counter 5 till the trailing edge of the input signal is shifted by one bit and is latched as the half value by the 1/2 latch 9. Then, the output signal of the circuit 1 is counted from the trailing edge of the input signal until it coincides with the output of the latch 9, and a coincidence signal is outputted.

8. 发明专利

JPS63192161A JAPANESE SENTENCE FORMING DEVICE 失效
公开(公告)号：JPS63192161A
公开(公告)日：1988-08-09
申请号：JP2583187
申请日：1987-02-05
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO
IPC分类号： G06F17/21 , G06F17/28
摘要： PURPOSE:To simply cope with the change in a data structure of the source of a sentence by sequentially taking out elements from the wooden construction type input data of the source of the Japanese sentence. CONSTITUTION:An input data holding device 101 for holding the wooden construction type input data of the source for forming the Japanese sentence, an input data extracting device 102 for sequentially extracting the respective elements in a sequence in which they are described in the input data and a Japanese sentence forming pattern storage device 103 in which the Japanese sentence forming pattern corresponding to the respective elements of the input data are provided. Further, a context searching device 104 for searching the context of the data held by an input data holding device 101 according to information received from the input data extracting device 102 and a Japanese output device 105 for outputting the Japanese according to information from the context searching device in accordance with the constituting elements of the Japanese sentence forming pattern are provided. Thereby, the output image of the Japanese sentence can be clarified only viewing the description and even when the change is generated in the data structure of the source of the sentence, it can be simply coped with.

9. 发明专利

JPS62118548A MOUNTING SUBSTRATE OF INTEGRATED CIRCUIT 失效
公开(公告)号：JPS62118548A
公开(公告)日：1987-05-29
申请号：JP25884685
申请日：1985-11-18
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO , YAMAZAKI TAKASHI
IPC分类号： H01L23/14 , H01L23/12 , H01L23/64 , H05K1/16
摘要： PURPOSE:To prevent local deviation of electric charge and to prevent a high potential at a local plate, by forming a highly resistive printed resistor film on the entire surface of a substrate except for electrodes and an integrated- circuit-chip attaching part of the substrate, thereby uniformly distributing the electric charge on the entire surface of the integrated-circuit mounting substrate and an IC. CONSTITUTION:A COB is formed as follows. An integrated-circuit chip 2 is mounted on an insulating substrate 1. Electrodes 3 are taken out of the integrated circuit chip and arranged on the insulating substrate. A highly-resistive printed resistor film 7 is formed on the entire surface except for an integrated- circuit-chip attaching part and the electrode on the substrate. Thus, the highly resistive (about 1MOMEGA/square) printed resistor is applied on the entire surface of the COB. Therefore the substrate of the COB and the IC become the almost equal potential.

10. 发明专利

JPH03197873A DETECTING CIRCUIT FOR POWER-SUPPLY VOLTAGE 失效
公开(公告)号：JPH03197873A
公开(公告)日：1991-08-29
申请号：JP33967589
申请日：1989-12-26
申请人： NEC CORP
发明人： SUGIYAMA TAKAHIRO
IPC分类号： G01R19/165 , G05F1/10
摘要： PURPOSE:To improve the detection accuracy of a power-supply voltage without trimming by supplying a current to a diode from a constant current source circuit. CONSTITUTION:When the power-supply voltage VDD at a power supply terminal TMP rises, the voltage at a node N1 connected to the plus-side input terminal of a comparator 2 rises in proportion to the voltage VDD since the voltage VDD is divided by resistances R1 and R2. The current which is supplied to the diode D1, on the other hand, is fixed as a constant current by a constant current source circuit 1, so the voltage at a node N2 is constant regardless of variation of the voltage VDD. The comparator 2 compares the voltage at the node N1 with the voltage at the node N2 to detect whether or not the voltage at the node N1 exceeds the voltage at the node N2, and outputs a high-level detection signal DET from its output terminal TM0 when the voltage exceeds, so the detection accuracy of the power-supply voltage can be improved without trimming.

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