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    • 6. 发明专利
    • COMPUTER CONTROLLING DEVICE
    • JPS6017537A
    • 1985-01-29
    • JP12441683
    • 1983-07-08
    • MITSUBISHI HEAVY IND LTD
    • MORIMOTO TADAKIYOIDE MIKIO
    • G06F9/30
    • PURPOSE:To improve the real time performance and to process the unpacking at a high speed by installing the data latch circuit, etc., preserving the logical data to which the data bath signal of the system bath is latched and packed. CONSTITUTION:The data latch circuit, etc., which preserve the logical data to which the data bath signal of the system bath are latched and packed, are installed. For example, by writing 1-word N-bit logical data to be unpacked in the data latch circuit 21 of the unpack processing part 10, the data latch strobing signal 32 is outputted, and the logical data 31 to be unpacked is preserved in the hardward. Next, by reading the port address corresponding to the bit position to be unpacked, the data select control signal 34 and gate control signal 37 are outputted, and the unpack data 36 is inputted in the computer. And, when all N- bit data is unpacked, the port address is changed after the data to be unpacked is written, and processing is executed by reading the data N times.