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1. 发明专利

JP2004260100A Diffusion region forming method for semiconductor device 审中-公开
公开(公告)号：JP2004260100A
公开(公告)日：2004-09-16
申请号：JP2003051546
申请日：2003-02-27
申请人： Mitsubishi Electric Corp , Renesas Semiconductor Engineering Corp , 三菱電機株式会社 , 株式会社ルネサスセミコンダクタエンジニアリング
发明人： YAHIRO JUNJI , YOSHIURA YASUHIRO
IPC分类号： H01L21/308 , H01L21/265
摘要： PROBLEM TO BE SOLVED: To provide a method for effectively etching the insulating film formed on a substrate when forming a diffusion region in the semiconductor substrate.
SOLUTION: A method for forming a diffusion region of a semiconductor device is a method for forming the diffusion region in the semiconductor substrate. The method contains the insulating film forming step of forming an insulating film (12) on a substrate (10), the etching step of decreasing a part of the insulating film (12) down to a predetermined thickness, the ion implantation step of implanting ions (16) into the substrate (10) through the insulating film (12) of the predetermined thickness, and the thermally processing step of thermally processing subsequent to the ion implantation step. Further, in the insulating film forming step, the insulating film (12) containing impurities is formed and its impurity density changes in response to a distance from the substrate (10) in a thickness direction of the insulating film (12).
COPYRIGHT: (C)2004,JPO&NCIPI

2. 发明专利

JP2011129622A High breakdown voltage semiconductor device 有权
标题翻译：高断电压半导体器件
公开(公告)号：JP2011129622A
公开(公告)日：2011-06-30
申请号：JP2009285109
申请日：2009-12-16
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KUSUNOKI SHIGERU , YAHIRO JUNJI , HIROTA YOSHIHIKO
IPC分类号： H01L27/04 , H01L21/336 , H01L29/06 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7397 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/16 , H01L27/0658 , H01L27/0761 , H01L29/0623 , H01L29/0661 , H01L29/404 , H01L29/8611 , H01L2224/0603 , H01L2224/48091 , H01L2224/49111 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2224/45099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress occurrence of a snap-back phenomenon in a high breakdown voltage semiconductor device in which an IGBT and a reflux diode are formed in a single semiconductor substrate. SOLUTION: A high breakdown voltage semiconductor device includes a semiconductor substrate 10, a p-type base region 11 in a first main surface 1, an n + -type emitter region 12 in the p-type base region 11, an n + -type cathode region 13 adjacent to an end surface of the semiconductor substrate 10 and not penetrating the semiconductor substrate 10, a p + -type collector region 14 in a second main surface 2, a first main electrode 41 coming into contact with the p-type base region 11 and n + -type emitter region 12, a second main electrode 42P coming into contact with the p + -type collector region 14, a third main electrode 43 coming into contact with the n + -type cathode region 13, and a connection means 42W connecting the second main electrode 42P and the third main electrode 43. A resistance R2 between the p-type base region 11 and the n + -type cathode region 13 is greater than a resistance R1 between the p-type base region 11 and the p + -type collector region 14. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：为了抑制在单个半导体衬底中形成IGBT和回流二极管的高耐压电压半导体器件中的快速反应现象的发生。解决方案：高耐压电压半导体器件包括半导体衬底10，第一主表面1中的p型基极区域11，p-型基极区域中的n + SP +型发射极区域12。类型基极区域11，与半导体衬底10的端面相邻并且不穿透半导体衬底10的n + SP + + / SP型阴极区域，第二主表面2中的区域14，与p型基极区域11和n + 型集电极区域14，与n + / SP>型阴极区域13接触的第三主电极43，以及连接第二主体电极42P和第三主电极43.p型基极区域11与n + SP型阴极区域13之间的电阻R2大于p型基极区域11之间的电阻R1 一个 d p + 型收集器区域14.版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2012199587A High-breakdown-voltage semiconductor device 有权
标题翻译：高电压半导体器件
公开(公告)号：JP2012199587A
公开(公告)日：2012-10-18
申请号：JP2012135706
申请日：2012-06-15
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KUSUNOKI SHIGERU , YAHIRO JUNJI , HIROTA YOSHIHIKO
IPC分类号： H01L29/06 , H01L21/336 , H01L27/04 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/868
摘要： PROBLEM TO BE SOLVED: To prevent occurrence of snapback phenomenon.SOLUTION: A high-breakdown-voltage semiconductor device comprises: a semiconductor substrate 10; a p-type base region 11; an n-type emitter region 12; n-type cathode regions 13 and p-type collector regions 14 that are alternately disposed adjacent to an end surface of the semiconductor substrate 10 side by side and are formed toward a second primary surface 2 from a first primary surface 1 with a depth not penetrating the semiconductor substrate 10; a trench region 36 that is adjacent to the end surface of the first primary surface 1 of the semiconductor substrate 10, is formed toward the second primary surface 2 from the first primary surface 1, and isolates the n-type cathode regions 13 and the p-type collector regions 14; a control electrode 40 that faces, via an interlayer insulating film 39, the p-type base region 11 sandwiched by the semiconductor substrate 10 and the n-type emitter region 12; a first main electrode 41 that contacts the p-type base region 11 and the n-type emitter region 12; and a second main electrode that is electrically connected to the n-type cathode regions 13 and the p-type collector regions 14.
摘要翻译：要解决的问题：为了防止发生回弹现象。解决方案：高耐压半导体器件包括：半导体衬底10; p型基区11; 一个n + 型发射器区域12; n + 型阴极区域13和p + 型集电极区域14，半导体衬底10并排并且从没有穿透半导体衬底10的深度的第一主表面1朝向第二主表面2形成; 从第一主表面1朝向第二主表面2形成与半导体衬底10的第一主表面1的端面相邻的沟槽区域36，并将n + 型阴极区域13和p + 型集电极区域14; 经由层间绝缘膜39与被半导体衬底10夹持的p型基极区域11和n + SP型发射极区域12面对的控制电极40; 接触p型基极区域11和n型发射极区域12的第一主电极41; 以及与n + 型阴极区域13和p + / SP>型集电极区域电连接的第二主电极 14.版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2011187880A Semiconductor device, and measurement method 有权
标题翻译：半导体器件和测量方法
公开(公告)号：JP2011187880A
公开(公告)日：2011-09-22
申请号：JP2010054383
申请日：2010-03-11
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： HIRAO MASAYOSHI , YAHIRO JUNJI
IPC分类号： H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L29/06 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of directly and easily measuring an electrical characteristic of an included diode, and a measurement method related to the semiconductor device. SOLUTION: This semiconductor device includes: an n - layer 6 and a p - layer 7; a guard ring 12; a channel stopper region 14; equipotential aluminum 15; and a collector electrode 8. The channel stopper region 14 is formed on a main surface of a semiconductor substrate to be located on an outer peripheral side of the guard ring 12. The equipotential aluminum 15 is electrically connected to the channel stopper region 14. The collector electrode 8 is formed on the back face of the semiconductor substrate. The semiconductor substrate includes the p - layer 7 and the n - layer 6. The p - layer 7 is electrically connected to the collector electrode 8. The n - layer 6 directly contacts the p - layer 7 and directly contacts the channel stopper region 14. The equipotential aluminum 15 includes a channel stopper electrode 16. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够直接容易地测量所包含的二极管的电特性的半导体器件以及与半导体器件相关的测量方法。解决方案：该半导体器件包括：n - 层6和p - 层7; 护环12; 通道停止区域14; 等电位铝15; 和集电极8.沟道阻挡区域14形成在半导体衬底的位于保护环12的外周侧的主表面上。等电位铝15与沟道阻挡区域14电连接。集电极电极8形成在半导体衬底的背面上。半导体衬底包括p - / SP>层7和n - / SP>层6.P - / SP>层7电连接到集电极8 n - 层6直接接触p - 层7，并直接接触通道阻挡区域14.等电位铝15包括通道阻挡电极16。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JPH04131373A SPUTTERING DEVICE 失效
公开(公告)号：JPH04131373A
公开(公告)日：1992-05-06
申请号：JP25246290
申请日：1990-09-21
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAHIRO JUNJI
IPC分类号： C23C14/34 , C23C14/50
摘要： PURPOSE:To allow washing with each of sputtering batches and to prevent the remaining of a reaction product to improve quality by forming a pallet of quartz and holding the above-mentioned pallet freely attachably and detachably in an external reinforcing body for preventing the misregistration with this pallet and reinforcing the pallet. CONSTITUTION:The surface material of the pallet 1 which is the element to generate the conductive material remaining after Al etching is investigated. The reaction product 11 which is the conductive material is not generated only when the surface material of the pallet is quartz as a result of the comparison made with 4 kinds of the surface materials of the pallet: SUS 316, quartz, the quartz deposited with an Al film, and SUS plate deposited with the Al film. Namely, the reaction product 1 which is the conductive material is not generated if the pallet 1 is formed of the quartz and is washed at every sputtering batch. The reinforcing plate 3A or reinforcing frame 3B having the construction shown in Fig. is used to allow the use of the quartz pallet in order to attain the above-mentioned prevention. In addition, the reinforcing plate 3A or reinforcing frame 3B is designed to allow the easy attachment and detachment thereof to and from the pallet 1 so as to allow the easier washing of the pallet 1.

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