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1. 发明专利

JP2006004203A Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：JP2006004203A
公开(公告)日：2006-01-05
申请号：JP2004180366
申请日：2004-06-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KISHIMOTO YOSHIHISA , URADE MASAKAZU , YASUTAKE KOICHI , OBAYASHI YOSHIMASA
IPC分类号： G06F12/08 , G06F9/46 , G06F12/12
摘要： PROBLEM TO BE SOLVED: To speed up media-based data processing by enabling data for media-based processing to be present on a cache memory without being influenced by caching operation of data for non-media-based processing. SOLUTION: This data processor comprises a cache memory 0101 exclusive for media-based processing and a cache memory 0102 exclusive for non-media-based processing. In transferring data to the cache memories, task kind information 0109 showing media-based processing or non-media-based processing is assigned thereto, and the transfer data are transferred to the corresponding cache memory according to the task kind information 0109 of the transfer data. According to this, data for media-based processing can be present in the cache memory 0101 exclusive for media-based processing regardless of the operation of newly registering data for non-media-based processing to the cache memory 0102 exclusive for non-media-based processing. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过使基于媒体的处理的数据能够存储在高速缓冲存储器上而不受用于非基于介质的处理的数据的高速缓存操作的影响来加速基于媒体的数据处理。解决方案：该数据处理器包括专用于基于媒体的处理的高速缓存存储器0101和专用于非基于媒体的处理的高速缓存存储器0102。在将数据传送到高速缓冲存储器时，分配表示基于媒体的处理或基于非媒体的处理的任务种类信息0109，根据传送数据的任务种类信息0109将传送数据传送到对应的高速缓冲存储器。据此，用于基于媒体的处理的数据可以存在于用于基于媒体的处理中的专用的高速缓存存储器0101中，而不管新注册非基于媒体的处理的数据的操作对于非媒体处理专用的高速缓存存储器0102，基于处理。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006172142A Multiprocessor system 审中-公开
标题翻译：多处理器系统
公开(公告)号：JP2006172142A
公开(公告)日：2006-06-29
申请号：JP2004363753
申请日：2004-12-16
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OBAYASHI YOSHIMASA , NAKAHARA MITSUNARI
IPC分类号： G06F13/38 , G06F15/167
CPC分类号： G06F13/24
摘要： PROBLEM TO BE SOLVED: To provide a multiprocessor system that eliminates redundancy in data assurance at data communication between respective processing parts. SOLUTION: At data communication between a network processing part 101 and a real time processing part 201, exclusive control of a shared memory is executed only by an output action of an interrupt signal of transmission completion from the transmitting network processing part 101 to the receiving real time processing part 201 and a detection action of the interrupt input of transmission completion at the receiving real time processing part 201, and data assurance against data garbling and data loss is executed only by TCP/IP protocol stack software 213. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种在各个处理部件之间的数据通信中消除数据保证冗余的多处理器系统。解决方案：在网络处理部分101和实时处理部分201之间的数据通信中，仅通过从发送网络处理部分101到发送完成的中断信号的输出动作来执行共享存储器的独占控制接收实时处理部201和接收实时处理部201的发送完成的中断输入的检测动作，仅通过TCP / IP协议栈软件213执行数据乱码和数据丢失的数据保证。
版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005151191A Portable terminal apparatus 有权
标题翻译：便携式终端设备
公开(公告)号：JP2005151191A
公开(公告)日：2005-06-09
申请号：JP2003386216
申请日：2003-11-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OBAYASHI YOSHIMASA , KAWAGUCHI KENICHI , URADE MASAKAZU
IPC分类号： H04M1/00 , H04B7/26
CPC分类号： Y02D70/00 , Y02D70/449
摘要： PROBLEM TO BE SOLVED: To predict a voltage value in the case of performing a task without conducting a pseudo-operation.
SOLUTION: A voltage change predicting means 60 receives notification from an input task notifying means 44 and calculates, as a prediction voltage value, a difference between a voltage value detected by a battery state detecting part 4 and the voltage value being reduced when a subsequent performance candidate task is performed, which is acquired by referring to a task power consumption characteristic table 50, When the prediction voltage value is lower than a power saving mode changeover threshold voltage value and higher than a power source off mode changeover threshold voltage value, a mask signal is output to a mode changeover mask part 30 so as not to changeover a mode into a power saving mode.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在不执行伪操作的情况下预测执行任务的情况下的电压值。电压变化预测单元60接收来自输入任务通知单元44的通知，计算由电池状态检测单元4检测出的电压值与正在减少的电压值之间的差值作为预测电压值执行随后的执行候选任务，其通过参考任务功耗特性表50获取。当预测电压值低于省电模式转换阈值电压值并高于电源关闭模式切换阈值电压值，将掩模信号输出到模式切换掩模部30，以便不将模式切换为省电模式。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2004258935A Semiconductor device 审中-公开
公开(公告)号：JP2004258935A
公开(公告)日：2004-09-16
申请号：JP2003048396
申请日：2003-02-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OBAYASHI YOSHIMASA
IPC分类号： G06F12/08 , G06F13/28
摘要： PROBLEM TO BE SOLVED: To solve the problem wherein there is the need to purge and invalidate a data cache prior to DMA (Direct Memory Accessing) transfer by a DMAC (Direct Memory Access Controller) for a CPU in order to maintain the coherency of data.
SOLUTION: A purge control part 160 which purges and invalidates the data cache 120 in place of the CPU 110 prior to the DMA transfer by the DMAC 150 is provided to reduce the burden on the CPU 110.
COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2004213414A Storage device control unit 审中-公开
公开(公告)号：JP2004213414A
公开(公告)日：2004-07-29
申请号：JP2003000435
申请日：2003-01-06
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： IWAMORI KOICHI , FUJINAWA IKUKO , OBAYASHI YOSHIMASA , KAWAGUCHI KENICHI
IPC分类号： G06F3/06 , G06F9/46 , G06F12/00
CPC分类号： G06F9/5027 , G06F2209/5017
摘要： PROBLEM TO BE SOLVED: To operate access from a plurality of tasks to a plurality of areas whose control methods are different on a storage device in parallel while maintaining real time performance.
SOLUTION: When tasks 101 and 102 perform access through file systems 103 and 105 to two data areas 109 and 107 of a storage device 110 whose control methods are different, an access arbitrating part 106 arbitrates an access request from the two file systems, and the access arbitrating part 106 divides data whose access is requested into access sector units of sizes large enough to maintain the real time performance of the tasks under operation, and the divided access requests are successively switched and the device access requests are issued to device control parts 108 and 104 corresponding to those respective data areas.
COPYRIGHT: (C)2004,JPO&NCIPI

6. 发明专利

JPH07282016A PARALLELING COMPILER 失效
公开(公告)号：JPH07282016A
公开(公告)日：1995-10-27
申请号：JP7222594
申请日：1994-04-11
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OBAYASHI YOSHIMASA
IPC分类号： G06F15/16 , G06F9/45
摘要： PURPOSE:To provide a compiler compiling a source program so that execution time in a parallel computer becomes the shortest. CONSTITUTION:This paralleling compiler is provided with a construction analysis means 3 performing a syntax analysis of the source program and converting it into an intermediate language, parallelism detection means 4 and 5 detecting loops which can be executed in parallel on the intermediate language and obtaining paralleling intermediate languages of all patterns in paralleling, an execution time evaluation means 6 predicting the execution time of the respective paralleling intermediate languages based on the loop frequency that the paralleling intermediate languages are executed in parallel, a part where the paralleling intermediate languages are executed in parallel and the number of processors which operate, a paralleling intermediate language selection means 7 selecting the paralleling intermediate language whose execution time predicted by the execution time evaluation means is the shortest and a target program generation means 8 converting the paralleling intermediate language selected by the paralleling intermediate language selection means 7 into the target program.

7. 发明专利

JPH10124453A CONTROL METHOD FOR RECEPTION OF BUS DEVICE CONNECTION REQUEST 失效
公开(公告)号：JPH10124453A
公开(公告)日：1998-05-15
申请号：JP27575996
申请日：1996-10-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OBAYASHI YOSHIMASA
IPC分类号： G06F13/362
摘要： PROBLEM TO BE SOLVED: To prevent such a case where the band that is used by every device is estimated smaller and the bands more than those of actually available buses are assigned to the devices. SOLUTION: When a connection request is received for a new bus device, an average bus using interval 4003 is reported together with an average bus occupation time 4001 needed when the longest burst transfer including not only the data transfer state but the bus occupied state is performed. Based on these report value, the propriety of permission is decided for connection of the bus device.

8. 发明专利

JPH09261645A IMAGE DATA EXPANDER 失效
公开(公告)号：JPH09261645A
公开(公告)日：1997-10-03
申请号：JP406697
申请日：1997-01-13
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OBAYASHI YOSHIMASA , KANEKO KATSUYUKI , MINO YOSHITERU , TOMITA SADAFUMI
IPC分类号： H04N19/60 , H03M7/30 , H04N1/41 , H04N19/423 , H04N19/44 , H04N19/503 , H04N19/577 , H04N19/61 , H04N19/625 , H04N7/30
摘要： PROBLEM TO BE SOLVED: To provide an image data expander expanding image data compressed via linear conversion at a high speed. SOLUTION: A non-null coefficient by one block obtained by decoding of an entropy decoding section 2024 is stored in an address of a coefficient storage section 121 according to a coordinate position calculated by a non-null coefficient scanning sequence calculation section 2023a and a non-null coefficient position conversion section 2023b. The stored non-null coefficient is subject to inverse quantization by an inverse quantization section 2022. A non-null coefficient range calculation section 122 discriminates areas of the coefficient storage section 121 where the non-null coefficients are stored. An arithmetic sequence control section 23 controls an inverse DCT section 2021 so that inverse DCT is applied only to the non-null coefficients in existence in the specified areas.

9. 发明专利

JPH11338815A BRIDGE DEVICE CAPABLE OF EVADING GRADATION OF BUS TRANSFER EFFICIENCY 失效
公开(公告)号：JPH11338815A
公开(公告)日：1999-12-10
申请号：JP17766398
申请日：1998-06-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OBAYASHI YOSHIMASA
IPC分类号： G06F13/28 , G06F13/36
摘要： PROBLEM TO BE SOLVED: To improve bus availability by preparing a means which outputs a request signal to an arbitration means to request the using right of a receiving bus after a transmitting device acquires the using right of a transmitting bus. SOLUTION: An address 103(3) is outputted to a primary local bus 1a after the using right of the bus 1a is acquired by a PCT-PCI bridge device 4. A target access part 7 tries to acquire the using right of the bus 1a to transfer the address via the bus 1a after a data bus started to fetch the address to a buffer. In other words, a request signal is outputted to an arbitration part 16 which arbitrates the bus 1a. Receiving the request signal, the part 16 outputs an enabling signal. When the part 7 acquires the using right of the bus 1a, the address can be outputted to the bus 1a via the data bus.

10. 发明专利

JPH10177542A BRIDGE DEVICE, COMPUTER SYSTEM USING THE DEVICE AND DATA TRANSFER METHOD FOR THE SYSTEM 失效
公开(公告)号：JPH10177542A
公开(公告)日：1998-06-30
申请号：JP33696696
申请日：1996-12-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OKABAYASHI ICHIRO , NISHIKAWA JUNJI , OBAYASHI YOSHIMASA
IPC分类号： G06F13/36 , G06F13/362
摘要： PROBLEM TO BE SOLVED: To surely carry out again the discontinued transfer of data by counting the discontinuation frequency of the discontinued, transfer of data when plural times of data transfer are requested and outputting a signal to an arbitration device to give the priority to the discontinued transfer of data when the discontinuation frequency reaches a prescribed level. SOLUTION: A computer system includes a host bus which is directly connected to a CPU, a primary local bus 4 which is connected to the CPU via a host bridge device, and a secondary local bus 6 which is connected to the bus 4 via a bridge device 5. The device 5 includes a count part 16 which counts the discontinuation signals which are outputted to the same master device from a control part 15a and an arbitration device 17 which arbitrates the using right of the bus 6. When the discontinuation frequency reaches a prescribed level, the part 15a outputs a priority use request signal to the device 17 to give the priority to the discontinued transfer of data.

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