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1. 发明专利

JPS60121725A ANNEALING METHOD FOR ION-IMPLANTED COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60121725A
公开(公告)日：1985-06-29
申请号：JP23096683
申请日：1983-12-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： TAKANO HIROZOU
IPC分类号： H01L21/265 , H01L21/324
摘要： PURPOSE:To obtain elements with less variation in electric characteristics by suffcient exhibition of the effect of proximity cap by a method wherein counter ions are implanted to the back surface of a compound semiconductor substrate bent convexly in the element-forming plane by the ion implantation for element formation, and the warp is corrected by the stress generating by the former ion implantation; then, two pieces of thus processed substrates are treated by annealing by contacting the respective element-forming planes. CONSTITUTION:Impurity ions I1 to give desired conductivity type are implanted to the element-forming plane of the compound semiconductor substrate 4, but the substrate 4 bends convexly toward the element-forming plane by the ion implantation. Therefore, the substrate 4 is flattened by correcting the warp by the implantation of counter ions I2 to the back surface thereof. Thereafter, the substrate 4 thus processed and a substrate 5 processed in the same manner are superposed on each other while the element-forming planes are contacted, which is then mounted on a graphite boat 1 and annealed. Thus ununiform thermal deformation in the substrate surface is inhibited, and the excellent effect of annealing is obtained.

2. 发明专利

JPS5891659A FORMING METHOD FOR ELECTRODE WIRING 失效
公开(公告)号：JPS5891659A
公开(公告)日：1983-05-31
申请号：JP19023281
申请日：1981-11-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： UOTANI SHIGEO , TAKANO HIROZOU
IPC分类号： H01L27/00 , H01L21/768 , H01L23/522 , H01L27/12
摘要： PURPOSE:To tide over the difficulties of technique forming a device by flattening electrode wiring without forming difference in stages of the end section of the wiring generated after shaping the electrode wiring. CONSTITUTION:A passivation film 4 is deposited without executing photoengraving at a point of time when an Al electrode film is formed to an SiO2 film 2 on a silicon single crystal substrate 1. Laser beams potically diaphragmed finely are accurately irradiated to regions except the electrode wiring. Accordingly, the temperature of the Al electrode of a section to be irradiated is elevated while oxygen is robbed from the film 4 and the film 2, and the films 4, 2 are oxidized instantaneously and changed into an Al2O3 film 9 in structure. Since the film 9 has high insulating characteristics, only Al wiring 3 holds conductivity, and a desirable wiring pattern can be shaped.

3. 发明专利

JPS5860544A GETTERING METHOD FOR CRYSTAL DEFECT 失效
公开(公告)号：JPS5860544A
公开(公告)日：1983-04-11
申请号：JP16064281
申请日：1981-10-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： TAKANO HIROZOU , MATSUKAWA TAKAYUKI
IPC分类号： H01L21/205 , H01L21/322
摘要： PURPOSE:To getter effectively defects induced by processes and the pollution by heavy metals by a method wherein a single crystal silicon film formed on an insulation film is made to have an effect of gettering. CONSTITUTION:Oxygen ions 4 of high dose are implanted uniformly into the whole of a polycrystalline silicon film 3 on an insulation film 2 formed on a single crystal silicon substrate 1, and then laser beams 5 of high output are applied on the whole thereof. The polycrystalline silicon film 3 is thereby transformed structurally into a single crystal silicon film 6, while the oxygen ions are diffused uniformly into the single crystal silicon film 6. When laser beams 5' of different output from that conditioning the monocrystallization are applied additionally to the single crystal silicon film 6, the oxygen existing on the uppermost surface of the film is diffused externally and a region 7 free from oxygen is formed on the surface thereof. Lastly it is annealed in a non-oxidizing ambience at the temperature of 600-800 deg.C and thereby a region 8 wherein minute defects having oxygen educt as nucleus, and a region 9 wherein no defect is generated, are foumed. Thus, only an active region wherein a device is formed is made free from defects, and the crystal defect and the pollution by heavy metal can be gettered by the minute defects generated in high density.

4. 发明专利

JPS57176730A FORMING METHOD FOR ULTRAFINE PATTERN 失效
公开(公告)号：JPS57176730A
公开(公告)日：1982-10-30
申请号：JP6290581
申请日：1981-04-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： MASUKO YOUJI , KOTANI KIYOUHIKO , TAKANO HIROZOU , HOSHIKA HARUYUKI
IPC分类号： H01L21/306
摘要： PURPOSE:To form an ultrafine pattern by performing wet etching under reduced pressure. CONSTITUTION:When an SiO2 formed on an Si substrate 1 is etched with a resist pattern 3 as a mask, it is performed in a reduced pressure container. Since the container 7 is reduced in pressure by an evacuated system 8, air bubbles on the resist pattern being hydrophobic can be readily removed. Accordingly, the creeping of the etchant becomes preferable, thereby obtaining desired ultrafine pattern. In addition, this invention can be applied even in case that the liquid is uniformly applied to the surface of the substance having weak hydrophilic property.

5. 发明专利

JPS5764932A Electron bean exposure device 失效
标题翻译：电子束曝光装置
公开(公告)号：JPS5764932A
公开(公告)日：1982-04-20
申请号：JP14074080
申请日：1980-10-07
申请人： Mitsubishi Electric Corp
发明人： TAKANO HIROZOU , SATOU SHINICHI , FUKUMOTO HAYAAKI , KOTANI HIDEO , HARADA KOUJI , KAYANO SHINPEI
IPC分类号： H01L21/027 , H01J37/317 , H01L21/30
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3177
摘要： PURPOSE:To improve the microminiature pattern drawing efficiency of a super LSI or the like by providing a plurality of electron guns, controlling a plurality of emitted electron beams by one control system and simultaneously drawing a plurality of patterns of the same size, configuration and disposition. CONSTITUTION:Stabilized high voltage is applied, for example, from a power source 1 to two electron guns 9a, 9b to simultaneously emit two high speed electron beams 10a, 10b. The electron beams 10a, 10b pass through lenses 4, 5, are thus converged to extremely small diameter are simultaneously deflected and scanned by a scanning coil, and two patterns are simultaneously drawn on the main surface of a wafer 7. After they are simultaneously drawn completely, a stage for supporting the wafer 7 is moved at the prescribed pitch, is sequentially scanned on undrawn region, and patterns are formed. In this manner, the drawing time of large bore wafer can be shortened, thereby enhancing the efficiency of forming the pattern with the electron beams.
摘要翻译：目的：通过提供多个电子枪来提高超级LSI等的微型图形绘图效率，通过一个控制系统控制多个发射的电子束，并同时绘制多个相同尺寸，配置和布置的图案。构成：例如从电源1向两个电子枪9a，9b施加稳定的高电压，同时发射两个高速电子束10a，10b。电子束10a，10b通过的透镜4,5因此会聚到非常小的直径，同时被扫描线圈偏转和扫描，并且在晶片7的主表面上同时绘制两个图案。完全地，用于支撑晶片7的阶段以规定间距移动，在未拉伸区域上被顺序地扫描，并且形成图案。以这种方式，可以缩短大孔晶片的拉伸时间，从而提高用电子束形成图案的效率。

6. 发明专利

JPS56108878A FORMATION FOR OPENING IN FILMLIKE SUBSTANCE 失效
公开(公告)号：JPS56108878A
公开(公告)日：1981-08-28
申请号：JP1184080
申请日：1980-02-01
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMANO TAKESHI , ARIMA HIDEAKI , TAKANO HIROZOU
IPC分类号： C23F1/00 , H01L21/302 , H01L21/306
摘要： PURPOSE:To form a desired tapered opening in a filmlike substance on a substrate without carrying out high-temp. treatment by implanting ions into the substance in a desired form to utilize a difference in etching resistance. CONSTITUTION:Insulating film 6 and photoresist film 7 are formed on semiconductor substrate 1. Part of film 7 is removed, film 7 is softened by heat treatment to form tapered opening 8, and predetermined ions are implanted to form tapered ion implanted region 9 corresponding to opening 8 in film 6. Film 6 is then etched using film 6 as a mask to expose part of substrate 1. At this time, since region 9 is easy to etch, it is removed quickly, and tapered opening 10 expanding toward the upper surface of film 6 is formed in film 6. Thus, the disconnection of wire or other trouble at the outer edge of opening 10 is prevented even if a wiring film is formed through opening 10 after removing film 7.

7. 发明专利

JPS52120562A REMOVING METHOD OF MICROOPARTICLE 失效
公开(公告)号：JPS52120562A
公开(公告)日：1977-10-11
申请号：JP3750676
申请日：1976-04-02
申请人： MITSUBISHI ELECTRIC CORP
发明人： TAKANO HIROZOU , NISHIOKA SUNAO
IPC分类号： B08B7/00 , B08B5/02 , H01L21/302
摘要： PURPOSE:To remove a micro-particle attaching onto the surface of a solid therefrom without damaging the surface using laser beam of an extremely small diameter.

8. 发明专利

JPS59217334A Annealing method of compound semiconductor substrate 失效
标题翻译：复合半导体衬底的退火方法
公开(公告)号：JPS59217334A
公开(公告)日：1984-12-07
申请号：JP9276083
申请日：1983-05-24
申请人： Mitsubishi Electric Corp
发明人： TAKANO HIROZOU
IPC分类号： H01L21/324
CPC分类号： H01L21/324
摘要： PURPOSE:To prevent reduction of cap effect by annealing two substrates the main surface of which is mirror-polished, ion-injected and warped in concave are placed facing each other with the main surface. CONSTITUTION:A pair of compound semiconductor substrate 4 and 5 wherein the main surface c and d are mirror-polished, ion-injected and concave are placed on a graphite board 1 and the main surfaces face each other. The substrates are annealed under these conditions and the main surfaces (c), (d) injected with ions are separated from the atmosphere in an annealing furnace. This expedites cap effect fully and enables restraining uneven thermal metamorphosis within the substrate surface whereby compound semiconductor elements which have less dispersion of electrical characteristics can be produced in high yield.
摘要翻译：目的：为了通过对其主表面进行镜面抛光的两个基板进行退火以防止帽盖效应的降低，离子注入并且在凹形中翘曲，以主表面彼此相对放置。构成：其中主表面c和d被镜面抛光，离子注入和凹入的一对化合物半导体衬底4和5放置在石墨板1上，并且主表面彼此面对。在这些条件下对基板进行退火处理，在退火炉中将离子注入的主表面（c），（d）与大气分离。这样可以充分地加速盖效应，并能够抑制基板表面内的不均匀的热变形，从而可以高产率地制造具有较小电特性分散性的化合物半导体元件。

9. 发明专利

JPS59141221A Annealing method of compound semiconductor substrate 失效
标题翻译：复合半导体衬底的退火方法
公开(公告)号：JPS59141221A
公开(公告)日：1984-08-13
申请号：JP1570283
申请日：1983-02-01
申请人： Mitsubishi Electric Corp
发明人： TAKANO HIROZOU
IPC分类号： H01L21/324 , H01L21/265
CPC分类号： H01L21/265
摘要： PURPOSE:To prevent a compound semiconductor substrate from generation of a pattern defect at annealing time by a method wherein compound semiconductor substrates of the plural number of pieces are stacked in the condition formed with thin film layers having the faculty of spacers, or interposed with spacers extending over the whole of the outer edge parts of the confronting surfaces of the substrate, and annealing is performed in an inactive or a hydrogen atmosphere. CONSTITUTION:Thin film layers 5, 6 are provided respectively to the outer edge parts of the confronting surfaces of GaAs substrates 1, 3 set in a circle. The thin film layers 5, 6 thereof are formed by performing high-frequency sputtering of SiO2, Si3N4, etc. through a metal mask, for example, and the thickness thereof is made thicker than thickness of fine patterns 2, 4 on the GaAs substrates 1, 3. When annealing is performed holding the GaAs substrates 1, 3 to confront mutually in such a condition, the thin film layers 5, 6 carry out the duty as spacers, both the fine patterns 2, 4 are not made to come in contact mutually, and eneration of wear and deformation is removed.
摘要翻译：目的：为了防止化合物半导体衬底在退火时产生图案缺陷，其方法是将多个片的化合物半导体衬底层叠在由具有间隔物的薄膜层形成的状态下，或者插入间隔物在衬底的相对表面的整个外边缘部分上延伸，并且在非活性或氢气气氛中进行退火。构成：将薄膜层5,6分别设置在设置为圆形的GaAs衬底1,3的相对表面的外边缘部分上。其薄膜层5,6通过例如通过金属掩模进行SiO 2，Si 3 N 4等的高频溅射而形成，并且其厚度比GaAs衬底上的精细图案2,4的厚度厚。当在这种状态下进行保持GaAs衬底1,3相互面对的退火时，薄膜层5,6执行作为间隔物的作用，两个精细图案2,4都不会进入相互接触，去除磨损和变形。

10. 发明专利

JPS5756036A Plasma chemical vapor phase reactor 失效
标题翻译：等离子体化学气相反应器
公开(公告)号：JPS5756036A
公开(公告)日：1982-04-03
申请号：JP13123480
申请日：1980-09-20
申请人： Mitsubishi Electric Corp
发明人： HARADA HIROJI , SATOU SHINICHI , FUKUMOTO HAYAAKI , TAKANO HIROZOU , KOTANI HIDEO , KAYANO SHINPEI
IPC分类号： B01J19/08 , C23C16/50 , H01J37/32 , H01L21/18 , H01L21/205
CPC分类号： H01J37/32623 , C23C16/50
摘要： PURPOSE:To improve the growth rate of films by providing magnets generating magnetic field parallel with the surface of the electrodes of a plasma chemical vapor phase reactor in the neighborhood of the surface of one of the electrodes of said device. CONSTITUTION:In a plasma chemical reactor producing semiconductor films such as silicon nitride films or the like, magnets 12, 12' are provided near the surface of one substrate 7, so that the magnetic lines 13 of force created by these are made parallel with the surface near the surface of a silicon wafer. Then, the electrons generated by plasma discharge are confined around said magnetic lines of force and therefore the density of plasma is icreased considerably near the magnetic lines of force, that is, on the surface of the silicon wafer, and the growth rate of the films is increased.
摘要翻译：目的：通过在所述装置的一个电极的表面附近提供与等离子体化学气相反应器的电极的表面平行的磁场，从而提高磁体的生长速度。构成：在制造诸如氮化硅膜等的半导体膜的等离子体化学反应器中，在一个基板7的表面附近设置磁体12,12'，使得由它们产生的力的磁线13与表面附近的硅晶片表面。然后，通过等离子体放电产生的电子被限制在所述磁力线周围，因此等离子体的密度显着地靠近磁力线，即在硅晶片的表面上，并且膜的生长速率增加了。

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