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1. 发明专利

JP2004158770A Method of predicting yield of semiconductor device and method of managing yield 审中-公开
公开(公告)号：JP2004158770A
公开(公告)日：2004-06-03
申请号：JP2002325179
申请日：2002-11-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIRASE JUNICHI , SASAKI TOMOYUKI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a method of predicting the yield of a semiconductor device by which the actual manufacturing yield of the semiconductor device can be predicted unlike the conventional method of predicting the manufacturing yield of the semiconductor device by which the actual yield is not able to be predicted, because the yield is found by considering the fault detection rate of faults occurring in the device as 100%.
SOLUTION: In this method, the yield of the semiconductor device is predicted by using the chip area of the device, the defect density of a step of manufacturing the semiconductor device, and the dispersion coefficient of average defect density. The manufacturing yield is predicted based on the fault detection rate showing the ratio of the number of faults which are detectable in an inspection step to the number of faults which have possibilities of occurring in the semiconductor device.
COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2001188807A TIME FAULT SIMULATION METHOD 失效
公开(公告)号：JP2001188807A
公开(公告)日：2001-07-10
申请号：JP37198199
申请日：1999-12-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SEZAKI TOMOHISA , HIRASE JUNICHI
IPC分类号： G01R31/28 , G01R31/3183 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a time fault simulation method by which whether or not a pertinent test pattern is provided with time fault inspection ability is verified for a time fault generated on a signal path inside a logic circuit for making signal change time fluctuate. SOLUTION: For the time fault generated on the signal path inside the logic circuit for making the signal change time fluctuate, prescribed time Δt is defined as the time fault, the signal change time on the signal path is delayed for the prescribed time Δt by the test pattern and circuit simulation is performed. Output signals from the logic circuit by the circuit simulation are compared with the output signal result of normal circuit simulation and when a difference between them is confirmed, it is defined that the time fault can be detected by the test pattern and it is defined that the time fault can not be detected by the test pattern when the difference can not be confirmed.

3. 发明专利

JPH085707A SEMICONDUCTOR DEVICE TESTING DEVICE 失效
公开(公告)号：JPH085707A
公开(公告)日：1996-01-12
申请号：JP13868194
申请日：1994-06-21
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MAEKAWA MICHIO , HIRASE JUNICHI
IPC分类号： G01R31/26 , G01R31/00 , G01R31/28
摘要： PURPOSE:To provide a semiconductor device testing device the testing time of which can be shortened. CONSTITUTION:Output voltage value measured data are stored in a measured data storing RAM 2 in the order of output terminal numbers and, when output data are accumulated by one hierarchy, the maximum value, minimum value, and mean value of the output data are calculated. Then the calculated maximum, minimum, and mean values are respectively stored in maximum, minimum, and mean value storing sections 4, 5, and 6 and respectively compared with reference values. Since the output voltage in another hierarchy can be measured and the measured data can be stored in the RAM 2 in parallel with the calculation of the maximum, minimum, and mean values, the testing time of a semiconductor testing device can be shortened.

4. 发明专利

JPS5836435B2 失效
公开(公告)号：JPS5836435B2
公开(公告)日：1983-08-09
申请号：JP13478678
申请日：1978-10-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： FURUTA MASAO , IZUMI YOSHIHIRO , CHIHARA HIROMITSU , KAJIHATA IWAHO , HIRASE JUNICHI
IPC分类号： G11C11/41 , G06F1/26 , G06F1/28 , G11C5/14 , G11C11/401 , G11C11/414

5. 发明专利

JP2004158771A Method of estimating defect level of semiconductor device 有权
公开(公告)号：JP2004158771A
公开(公告)日：2004-06-03
申请号：JP2002325181
申请日：2002-11-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIRASE JUNICHI , KAMATANI YASUHIRO
IPC分类号： H01L21/66 , H01L21/02
摘要： PROBLEM TO BE SOLVED: To provide a method by which the defect level of a semiconductor device which is an index showing the overlooking rate of shipping defective semiconductor devices can be estimated when the semiconductor device is manufactured, and a formula on an effective defect level which well agrees with a market fraction defective logically caused by inspections performed at a manufacturing site can be calculated by deducing a relational expression between the length of a test pattern and a fault recognition rate.
SOLUTION: A formula on a defect level is deduced by calculating the yield of the semiconductor device and using a fault distribution function having the same characteristics of those of a defect distribution function by assuming that faults themselves also have distribution functions, because the faults are the defects showing cleared-up physical phenomena.
COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2001141793A SEMICONDUCTOR INSPECTION DEVICE AND SEMICONDUCTOR INSPECTION METHOD 失效
公开(公告)号：JP2001141793A
公开(公告)日：2001-05-25
申请号：JP32620699
申请日：1999-11-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUMOTO ASAKO , HIRASE JUNICHI , MATSUMOTO MASAHIKO
IPC分类号： G01R29/08 , G01R31/00 , G01R31/30
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor inspection device and a semiconductor inspection method securing the compatibility of both electromagnetic environment and normal operation in a semiconductor device to improve the quality of the semiconductor device, and not requiring a dedicated board and device for every semiconductor device for estimating the electromagnetic environment compatibility to reduce the development man-hours and the cost of the semiconductor device. SOLUTION: This general-purpose semiconductor inspection device has a configuration and a method for inspection for securing the normal operation and an electromagnetic interference property measurement device 12 and an electromagnetic interference property measurement method for inspection for securing an electromagnetic interference property. Thereby, the semiconductor inspection device can inspect the normal operation and the electromagnetic interference property of the semiconductor device 1 in the same one process when executing shipment inspection.

7. 发明专利

JP2000304826A FAILURE POSITION DETECTION DEVICE FOR SCAN CHAIN 失效
公开(公告)号：JP2000304826A
公开(公告)日：2000-11-02
申请号：JP11848199
申请日：1999-04-26
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SHINDO NAOKI , NAKAI IWAO , HIRASE JUNICHI
IPC分类号： G06F11/22 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To judge whether a failure exists or not as well as locate a failure position on a 'scan chain' in a scan chain test. SOLUTION: When a pulse data is transmitted to a 'scan chain' in a device designed by, a maximum or a minimum occurs in an IDDQ if a failure exists on the scan chain. So the maximum or the minimum of the IDDQ is detected by an IDDQ measuring means 8 for detecting the failure position with the time when the maximum or the minimum occurs.

8. 发明专利

JPH11297093A METHOD OF INSPECTING SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH11297093A
公开(公告)日：1999-10-29
申请号：JP9337498
申请日：1998-04-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIYASAKO KAZUNOBU , HIRASE JUNICHI
IPC分类号： G01R31/28 , G11C29/00 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To make it possible to detect a decoder transition failure in an N-type pattern with the inspection time simply proportional to the memory capacity of a semiconductor memory and greatly reduce the inspection time by doing the write and read only for designated address and inverted address thereof to detect the decoder transition failure of the memory. SOLUTION: The method of inspecting a semiconductor memory comprises writing '0' in all memory cells, repeating the write and read operations for an interest cell address and inverted address thereof the most severe as a decoder transition operation of the semiconductor memory, starting from the top address to the last address, then writing '1' in all the memory cells and similarly repeating the write and read operation from the last address to the top address, thus ending the inspection. According to this method the inspection time is simply proportional to the memory capacity of the semiconductor memory.

9. 发明专利

JPH11133101A STATIONARY POWER SUPPLY CURRENT TEST CIRCUIT 失效
公开(公告)号：JPH11133101A
公开(公告)日：1999-05-21
申请号：JP29219597
申请日：1997-10-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MAEKAWA MICHIO , HIRASE JUNICHI
IPC分类号： G01R31/26 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To accurately measure the abnormal current value of a power supply current caused by the defect of an internal circuit by dividedly measuring the stationary power supply current test. SOLUTION: This test circuit is provided with small-scale CMOS circuits 1-3 using low-threshold value voltage transistors, switches 4-5 using high- threshold value voltage transistors inserted between the power supply terminals and GND of the CMOS circuits 1-3, pull-down circuits 7 fixing the CMOS inputs of the small-scale circuits 1-3, and a selector 10 selecting the small-scale circuit measuring a stationary power supply current. Large-scale CMOS circuits can be divided to measure the stationary power supply current, thereby the effect of the leakage current of the low-threshold value voltage transistors can be minimized. The measurement of the stationary power supply current which has been difficult by conventional low-voltage, large-scale CMOS circuits using the low-threshold value voltage transistors is made feasible, and good product/ defective products can be judged by a stationary power supply current test in a shipping inspection.

10. 发明专利

JPH10267988A SEMICONDUCTOR TESTER 失效
公开(公告)号：JPH10267988A
公开(公告)日：1998-10-09
申请号：JP7140397
申请日：1997-03-25
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIYASAKO KAZUNOBU , HIRASE JUNICHI
IPC分类号： G01R31/26 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To test a semiconductor integrated circuit accurately by supplying each power supply system terminal with an individual voltage generated based on a reference voltage and voltages received at individual power supply system terminals thereby suppressing fluctuation among the individual voltages. SOLUTION: A semiconductor tester 1A comprises voltage control circuits 21, 22 receiving the voltages at power supply voltage terminals VP1, VP2 to be tested by switching relay circuits 81, 82 and supplies the terminals VP1, VP2 with individual voltages V1, V2 generated based on these voltages and a reference voltage VS. A voltage control circuit 25 receives a voltage from a ground terminal GP by switching a relay circuit 85 and generates an individual ground voltage G2 being fed to the terminal GP. The individual voltages V1, V2 and the individual ground voltage G2 are fed to a semiconductor circuit 7 to be measured which is also fed with a specified signal among signals S1-Sn from a select circuit 50 and a signal is selected from the circuit 7 and fed to a current/voltage measuring unit 60. The measuring unit 60 delivers the current and voltage vales of a measured signal to an apparatus control circuit 90.

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