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1. 发明专利

JP2006086754A Tuner card, host device, and receiver 有权
标题翻译：调音卡，主机设备和接收器
公开(公告)号：JP2006086754A
公开(公告)日：2006-03-30
申请号：JP2004268817
申请日：2004-09-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ADACHI TATSUYA
IPC分类号： H04B1/16 , H04H1/00 , H04H20/00 , H04H60/23 , H04L9/10 , H04N7/167 , H04N21/418
摘要： PROBLEM TO BE SOLVED: To provide an inexpensive receiver for protecting a copyright of contents data and to provide a tuner card for configuring the receiver and a host device.
SOLUTION: The tuner card is provided with: a tuner for demodulating stream data including encrypted contents and a encrypted scramble key from a broadcast wave; a key decryption unit for decrypting the scramble key; and a host interface section that transmits the stream data to the host device, receives the encrypted scramble key transmitted from the host device and transmits the scramble key to the key decryption unit, and transmits the decrypted scramble key outputted from the key decryption unit to the host device.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于保护内容数据的版权的便宜的接收机，并提供用于配置接收机和主机设备的调谐器卡。调谐器卡提供有：用于从广播波解调包括加密内容的流数据和加密的加扰密钥的调谐器; 用于解密加密密钥的密钥解密单元; 以及主机接口部分，其将流数据发送到主机设备，接收从主机设备发送的加密的加密密钥，并将加扰密钥发送给密钥解密单元，并将从密钥解密单元输出的解密密钥发送到主机设备。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2003036202A Storage device 有权
标题翻译：储存设备
公开(公告)号：JP2003036202A
公开(公告)日：2003-02-07
申请号：JP2001223575
申请日：2001-07-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： IZUMI TOMOAKI , IWATA KAZUYA , KASAHARA TETSUSHI , ADACHI TATSUYA , SHIYOURAIDEN JUICHI , HONDA TOSHIYUKI
IPC分类号： G11C16/02 , G06F1/04 , G06F1/08 , G06F12/00 , G06K17/00 , G06K19/07
CPC分类号： Y02D10/13
摘要： PROBLEM TO BE SOLVED: To provide a storage device which reduces power consumption caused for the generation of a clock signal, and improves data processing speed. SOLUTION: A command identification part 1a in a host interface 1 identifies a command from a host H, and outputs the command identification information as a command identification signal ID to a clock frequency decision part 5. The clock frequency decision part 5 determines a set frequency f of a clock signal CLK2 in response to the command identification information. As a result, the data processing speed of a storage element control part 2 is varied for each command.
摘要翻译：要解决的问题：提供一种降低由于产生时钟信号而引起的功耗并且提高数据处理速度的存储装置。解决方案：主机接口1中的命令识别部分1a识别来自主机H的命令，并将命令识别信息作为命令识别信号ID输出到时钟频率判定部件5.时钟频率判定部件5确定设定频率 f的响应于命令识别信息的时钟信号CLK2。结果，对于每个命令，存储元件控制部分2的数据处理速度是变化的。

3. 发明专利

JP2001357612A RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JP2001357612A
公开(公告)日：2001-12-26
申请号：JP2000176898
申请日：2000-06-13
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ADACHI TATSUYA
IPC分类号： G11B20/10 , G11B19/02
摘要： PROBLEM TO BE SOLVED: To improve the drop of the use efficiency of a recording medium such as an optical disk when sound data is recorded without compression, or after compression by leaving a data rate as high as it is for increasing dubbing speed. SOLUTION: (1) A signal recorded without compression is read, is recorded after compression and data of non-compression, whose recording is completed, are sequentially deleted. (2) The signal recorded by a compression method exceeding the prescribed data rate is read and expanded. The signal is recorded after compression by the compression method by making it to the prescribed data rate. Compression data whose recording is completed and which have the high data rate are sequentially deleted.

4. 发明专利

JP2000339864A DISK REPRODUCING DEVICE 失效
公开(公告)号：JP2000339864A
公开(公告)日：2000-12-08
申请号：JP14840099
申请日：1999-05-27
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： IZUMI TOMOAKI , ADACHI TATSUYA , HATANAKA MASAHIKO , MATSUNO KIMINORI
IPC分类号： G11B20/10
摘要： PROBLEM TO BE SOLVED: To enable the immediate start of an audio output by preventing the interruption of the audio output at the time of moving from the normal reproduction to the operation of fast forwarding reproduction or the fast running reproduction. SOLUTION: This disk reproducing device is provided with a memory means 4 for temporarily storing the audio data read out from a disk medium 1, a reproducing output means 5 for reading out the audio data therefrom and outputting them, and a system control means 8 for intermittently reading out the audio data at the time of operating the fast forwarding reproduction. By this system control means 8, the audio data for normal reproduction stored in the memory 4 are read out in the manner of thinning out in the fast forwarding direction with the specified interval and outputted as a 1st reproducing output data, and also the audio data for fast forwarding reproduction are intermittently read out from the disk medium succeeding to the audio data for normal reproduction and stored in the memory means 4, and after the output of the 1st reproducing output data is finished, the succeedingly stored intermitent audio data are read out from the memory means 4 as a 2nd reproducing output data and outputted.

5. 发明专利

JPH0817145A PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0817145A
公开(公告)日：1996-01-19
申请号：JP26359494
申请日：1994-10-27
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HORI MASATOMO , ADACHI TATSUYA , KATOU NOBUYOSHI , EJIMA NAOKI , EMA NORIYUKI , TAKAMA KAZUO
IPC分类号： G11B20/14
摘要： PURPOSE:To obtain a phase synchronizing circuit which has a wide capture range and responds quickly except in a vibrational environment and which is resistant against noise under the other environment. CONSTITUTION:It is decided that a phase synchronizing circuit is in a vibrational environment from the output value of a low-pass filter 110 and a period datum which is supplied to an oscillation unit 107 is switched from a fixed value CTC to the output value of the low-pass filter 110. With this constitution, both a following performance and a noise resistance can be improved. Further, a predetermined time constant can be given to the above decision. Moreover, by declining the cutoff of the low-pass filter at the time of the above decision, a stable operation can be realized. Also, under the vibration environment, the integral element of a loop filter 1100 is eliminated to improve the response characteristics in a high frequency range. Or, by clearing a memory means of which the above mentioned integral element is composed, error deterioration at the time of switching can be avoided.

6. 发明专利

JPH07296520A PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH07296520A
公开(公告)日：1995-11-10
申请号：JP8957194
申请日：1994-04-27
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HORI MASATOMO , TAKAMA KAZUO , EJIMA NAOKI , ADACHI TATSUYA , EMA NORIYUKI , KATOU NOBUYOSHI
IPC分类号： G11B20/10
摘要： PURPOSE:To provide a phase synchronizing circuit with a wide capture range and high speed response and capable of always providing an excellent reproducing sound even under vibrational environment. CONSTITUTION:A frequency of a clock generated by an oscillation part 6 is decided by bit rate information being an output of a bit rate detection part 7, and the phase of the generated clock is delayed or advanced according to phase error information between the edge of the generated clock being the output of a phase comparison part 4 and zero cross information. By such a manner, the phase error information takes no large value even for remarkable bit rate fluctuation. Further, since the bit rate detection part 7 calculates the common bit rate information from (n) pieces of self synchronizing signals, the number of samples are much, and the precise bit rate information is obtained.

7. 发明专利

JPH0685120B2 失效
公开(公告)号：JPH0685120B2
公开(公告)日：1994-10-26
申请号：JP8850183
申请日：1983-05-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MURASE KAZUHIRO , ADACHI TATSUYA , KAWAMOTO KINJI
IPC分类号： G10H1/053 , G10H7/00 , G10H7/02 , G10H7/08

8. 发明专利

JPH04321988A TOC RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH04321988A
公开(公告)日：1992-11-11
申请号：JP9200491
申请日：1991-04-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ADACHI TATSUYA
IPC分类号： G11B15/44 , G11B15/087 , G11B20/12 , G11B23/36 , G11B27/00 , G11B27/28 , G11B27/32
摘要： PURPOSE:To shorten time required for TOC search by recording TOC on both A side and B side CONSTITUTION:On the A side of a tape, three program numbers from 1 to 3 are recorded, and on the B side, two program numbers from 4 to 5 are recorded. And, an absolute time, A-TIME, is recorded continuously from the starting point of the program 1 on the A side to the completing point of the program 5 on the B side, and the absolute time of the completing point D of the program 3 and the absolute time of the starting point E of the program 4 are set on the same value. In addition, at the record completing point on the A side, a reverse marker RMK indicating a record starting point on the B side continuously exists following this completing point is recorded, and at the record starting point on the B side, the similar marker RMK is recorded.

9. 发明专利

JPH04155661A DATA REPRODUCING UNIT 失效
公开(公告)号：JPH04155661A
公开(公告)日：1992-05-28
申请号：JP28008890
申请日：1990-10-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ADACHI TATSUYA
IPC分类号： G11B20/10 , G11B27/28
摘要： PURPOSE:To realize positive detection of a search mark at the time of high speed searching operation by detecting data based on a detected run length and a stored run length. CONSTITUTION:A system control section 105 takes in run length information from an envelope demodulating section 108 and stores run length information of a frame, which is decided to be provided with no start ID nor a read out area ID, in a normal frame run length memory section 111. Updated run length information LL fed from the demodulating section 108 is then checked and when it is larger than ten times of the run length P of a normal frame storing the information LL, a tape run stop command is fed to a mechanism control section 102 and the information LL is substituted for the P in the memory section 111 when the information LL is in the range of 2.5-10 times of the run length P. When the run length of normal frame is constantly updated and thus updated value is employed in the estimation of the run length of a new frame, an envelope can be demodulated accurately.

10. 发明专利

JPH03156773A RECORDING DEVICE, REPRODUCING DEVICE AND RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH03156773A
公开(公告)日：1991-07-04
申请号：JP29586389
申请日：1989-11-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ADACHI TATSUYA
IPC分类号： G11B20/10
摘要： PURPOSE:To attain read-after-write processing at a high transfer rate by using plural number of recording sections and reproducing sections having a low processing speed and operating them in parallel. CONSTITUTION:A rate conversion section 107 converts recording signals SRRFR and SRRFRS outputted from recording sections 108, 109 into a recording signal SRRF2 of a double rate and outputs the result, converts a reproduction signal PBDT2 outputted from a head signal processing section 106 into reproduction signals PBDTP and PBDTQ of the standard transfer rate and supplies the result to reproduction sections 110, 111. Then two each of the recording sections 108, 109 and the reproduction sections 110, 111 and one RAM (random access memory) are used for the recording and reproduction respectively and operated in parallel to apply recording and reproduction at a transfer rate twice the transfer rate realized substantially by the recording sections 108, 109 and the reproduction sections 110, 111 simultaneously. Thus, the read-after-write processing at a high transfer rate is attained.

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