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1. 发明专利

JP2014002767A Efficient parallel floating point exception processing by processor 审中-公开
标题翻译：加工者有效的平行浮点处理
公开(公告)号：JP2014002767A
公开(公告)日：2014-01-09
申请号：JP2013161489
申请日：2013-08-02
申请人： Intel Corp , インテルコーポレイション
发明人： SPERBER ZEEV , FINKELSTEIN SHACHAR , PRIBUSH GREGORY , GRADSTEIN AMIT , BALE GUY , PONS THIERRY
IPC分类号： G06F7/76 , G06F7/483 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： PROBLEM TO BE SOLVED: To efficiently process a floating point exception by a processor which executes an SIMD instruction.SOLUTION: Processing includes the steps of: specifying a numeral exception of an SIMD floating point operation; starting a first SIMD micro operation so as to generate a first Packed part result of the SIMD floating point operation; starting a second SIMD micro operation so as to generate a second Packed part result of the SIMD floating point operation; starting an SIMD unnormalization micro operation so as to put the first and second Packed part results together and to generate a third Packed result having an unnormalized element by unnormalizing a first element of the first and second Packed part results having been put together; storing the third Packed result of the SIMD floating point operation; and setting a flag for specifying the unnormalized element of the third Packed result to the first Packed part result.
摘要翻译：要解决的问题：通过执行SIMD指令的处理器有效地处理浮点异常。解决方案：处理包括以下步骤：指定SIMD浮点运算的数字异常; 开始第一SIMD微操作，以产生SIMD浮点运算的第一打包部分结果; 开始第二SIMD微操作，以产生SIMD浮点运算的第二打包部分结果; 开始SIMD非归一化微操作，以将第一和第二填充部分结果合并在一起，并通过将已经放在一起的第一和第二填充零件结果的第一元素非规范化来生成具有非归一化元素的第三填充结果; 存储SIMD浮点运算的第三个打包结果; 并且将用于将第三打包结果的非标准化元素指定为第一包装部分结果的标志。

2. 发明专利

JP2010020761A Efficient parallel floating-point exception handling in processor 审中-公开
标题翻译：处理器中有效的平行浮点处理处理
公开(公告)号：JP2010020761A
公开(公告)日：2010-01-28
申请号：JP2009152985
申请日：2009-06-26
申请人： Intel Corp , インテルコーポレイション
发明人： SPERBER ZEEV , FINKELSTEIN SHACHAR , PRIBUSH GREGORY , GRADSTEIN AMIT , BALE GUY , PONS THIERRY
IPC分类号： G06F7/00
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： PROBLEM TO BE SOLVED: To efficiently handle floating-point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. SOLUTION: A method is provided for handling the floating-point exceptions in the processor that executes the SIMD instructions. The method includes: a step of initiating a first SIMD micro-operation to generate first packed partial results of the SIMD operation; a step of initiating a second SIMD micro-operation to generate second packed partial results of the SIMD operation; a step of initiating a SIMD denormalization micro-operation to combine the first and the second packed partial results and to generate third packed results having denormalized elements by denormalizing a first element of first and second packed partial results; a step of storing third packed results of the SIMD operation; and a step of setting a flag to identify denormalized elements of the third packed results in the first packed partial results. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：有效处理执行单指令多数据（SIMD）指令的处理器中的浮点异常。解决方案：提供了一种处理执行SIMD指令的处理器中的浮点异常的方法。该方法包括：启动第一SIMD微操作以产生SIMD操作的第一打包部分结果的步骤; 启动第二SIMD微操作以产生SIMD操作的第二打包部分结果的步骤; 启动SIMD非规范化微操作以组合第一和第二打包部分结果并通过对第一和第二打包部分结果的第一元素进行非归一化来生成具有非归一化元素的第三打包结果的步骤; 存储SIMD操作的第三打包结果的步骤; 以及设置标志以识别第一打包部分结果中的第三打包结果的非规范化元素的步骤。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2013050965A Efficient parallel floating point exception handling in processor 审中-公开
标题翻译：处理器中有效的平行浮点处理处理
公开(公告)号：JP2013050965A
公开(公告)日：2013-03-14
申请号：JP2012222612
申请日：2012-10-05
申请人： Intel Corp , インテルコーポレイション
发明人： SPERBER ZEEV , FINKELSTEIN SHACHAR , PRIBUSH GREGORY , GRADSTEIN AMIT , BALE GUY , PONS THIERRY
IPC分类号： G06F7/76 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： PROBLEM TO BE SOLVED: To efficiently handle floating point exceptions in a processor that executes SIMD instructions.SOLUTION: The method comprising: identifying a numerical exception for a SIMD floating point operation; initiating a first SIMD micro-operation to generate a first packed partial result for the SIMD floating point operation; initiating a second SIMD micro-operation to generate a second packed partial result for the SIMD floating point operation; initiating a SIMD denormalization micro-operation to combine the first and second packed partial results and to denormalize a first element of the combined first and second packed partial results to generate a third packed result having a denormal element; storing the third packed result for the SIMD floating point operation; and setting a flag identifying the denormal element of the third packed result in the first packed partial result.
摘要翻译：要解决的问题：有效处理执行SIMD指令的处理器中的浮点异常。解决方案：该方法包括：识别SIMD浮点运算的数字异常; 启动第一SIMD微操作以产生用于SIMD浮点运算的第一打包部分结果; 启动第二SIMD微操作以产生用于SIMD浮点运算的第二打包部分结果; 启动SIMD非规范化微操作以组合所述第一和第二打包部分结果，并且对所述组合的第一和第二打包部分结果的第一元素进行非规范化，以生成具有反正态元素的第三打包结果; 存储用于SIMD浮点运算的第三打包结果; 以及在第一打包部分结果中设置标识第三打包结果的异常元素的标志。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2007183942A Processor having inactive operation status and method for it 有权
标题翻译：具有不活动操作状态的处理器及其方法
公开(公告)号：JP2007183942A
公开(公告)日：2007-07-19
申请号：JP2006348280
申请日：2006-12-25
申请人： Intel Corp , インテルコーポレイション
发明人： GILA KAMHI , ZELIG WAYNER , AMIT GRADSTEIN , YAGIL YOAD , PONS THIERRY , ITTAI ANATI , FRAER RANAN
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： PROBLEM TO BE SOLVED: To provide a processor having an effective inactive operation status and a method for it. SOLUTION: Before the inactive operation status is started after determining whether the inactive operation status should be started or not, one or more micro operation sequences are carried out by one or more execution units. COPYRIGHT: (C)2007,JPO&INPIT

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