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1. 发明专利

JP2003282809A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003282809A
公开(公告)日：2003-10-03
申请号：JP2002077740
申请日：2002-03-20
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO FUJIO , SUZUKI HIROMICHI
IPC分类号： H01L21/56 , H01L21/44 , H01L21/48 , H01L23/48 , H01L23/495 , H01L23/50 , H01L23/52 , H01L29/40
CPC分类号： H01L24/85 , H01L21/4878 , H01L23/49541 , H01L23/49555 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/97 , H01L2224/05554 , H01L2224/05599 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/85399 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/48465 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To improve the mounting reliability of a multi-pin QFN (Quad Flat Non-leaded package) and to reduce its manufacturing cost. SOLUTION: A die pad 4 mounted with a semiconductor chip 2 is arranged at the center of a sealing body 3 composing a package of the QFN1. A plurality of leads 5 are arranged so as to surround the die pad 4. One ends 5a of the leads 5 are each electrically connected to a bonding pad on the main surface of a semiconductor substrate 2 through the intermediary of an Au wire 6, and the other ends 5c of the leads 5 each terminate at the side face of the sealing body 3. External connection terminals 5d formed by partially bending the leads 5 by a press protrude outward from the rear surface of the sealing body 3, and a solder layer 9 is formed on each surface of the terminal 5d. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提高多引脚QFN（四方扁平无铅封装）的安装可靠性，并降低其制造成本。解决方案：安装有半导体芯片2的管芯焊盘4布置在构成QFN1的封装的密封体3的中心。多个引线5被布置成围绕芯片焊盘4.引线5的一端5a通过Au导线6与半导体衬底2的主表面的接合焊盘电连接，并且引线5的另一端5c各自在密封体3的侧面终止。通过压力部分地弯曲引线5形成的外部连接端子5d从密封体3的后表面向外突出，并且焊料层 9形成在端子5d的每个表面上。版权所有（C）2004，JPO

2. 发明专利

JP2003303919A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003303919A
公开(公告)日：2003-10-24
申请号：JP2002108086
申请日：2002-04-10
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , Hitachi Yonezawa Electronics Co Ltd , 日立米沢電子株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MIYAKI YOSHINORI , SHIMANUKI YOSHIHIKO , SUZUKI HIROMICHI , ITO FUJIO
IPC分类号： H01L23/12 , H01L21/56 , H01L21/60 , H01L21/68 , H01L23/31 , H01L23/50 , H01L25/04 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/568 , H01L21/561 , H01L21/566 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/0657 , H01L2221/68331 , H01L2224/05554 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48245 , H01L2224/48247 , H01L2224/49171 , H01L2224/85001 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06582 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/07802 , H01L2924/10162 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a non-lead, plastic molded type semiconductor device that is thin, small-sized, and low-priced. SOLUTION: The device is a semiconductor device fabricated by arranging a flexible tape on the product forming part of the main surface with the multiple terminals, set freely detachably via a first binding material, freely detachably fixing the semiconductor device to the main surface of the tape via a second binding material, connecting the electrode of the semiconductor device and the terminals with electrically-conductive wires, forming an insulating resin layer in the sphere, including the semiconductor device and the wires on the main surface of the tape to cover the semiconductor device and the wires, and detaching the tape on the reverse of the insulating resin layer, thus forming the terminals that appear on the backside of the insulating resin layer. The exposed surface of the terminals is formed from a metal. The terminals are formed, by forming one or more subsidiary metal layers on the main and back surfaces of the main metal layer composed of copper foils. The subsidiary metal layer on the main surface side of the main metal layer is formed by using of a material that makes the surface rough to form the surface of the main surface side of the terminals. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种薄型，小型和低价的非铅塑料模制型半导体器件。解决方案：该器件是通过在形成主表面的产品上的柔性带与多个端子布置而制成的半导体器件，其通过第一粘合材料自由地可拆卸地设置，将半导体器件自由地可拆卸地固定到主表面通过第二捆扎材料将所述半导体器件的电极和所述端子与导电线连接，在所述球体中形成绝缘树脂层，所述绝缘树脂层包括所述半导体器件和所述带的主表面上的导线以覆盖半导体器件和电线，并且在绝缘树脂层的背面分离带，从而形成出现在绝缘树脂层的背面上的端子。端子的暴露表面由金属形成。通过在由铜箔构成的主金属层的主表面和背面上形成一个或多个辅助金属层而形成端子。主金属层主表面侧的辅助金属层通过使表面粗糙化形成端子的主表面侧的表面的材料形成。版权所有（C）2004，JPO

3. 发明专利

JP2003068965A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2003068965A
公开(公告)日：2003-03-07
申请号：JP2001261824
申请日：2001-08-30
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KUSUKAWA JUNPEI , TAKEUCHI RYOZO , ISHII TOSHIAKI , SUZUKI HIROMICHI , ITO FUJIO , NISHIDA TAKAFUMI , KAMEOKA AKIHIKO , YAMADA MASARU
IPC分类号： H01L23/50 , H01L23/00 , H01L23/28 , H01L23/31 , H01L23/433 , H01L23/495 , H01L23/498
CPC分类号： H01L23/564 , H01L23/3128 , H01L23/4334 , H01L23/49582 , H01L23/49816 , H01L23/49866 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of a trouble such as leakage, short- circuiting, etc., caused by ion migration in a semiconductor device. SOLUTION: The semiconductor device is assembled by using a lead frame with heat sink which is constituted by bonding inner leads 1a composed of copper or copper alloys to a heat sink 3 through an adhesive layer 2 formed on the surface of the heat sink 3 and plating at least parts of the inner leads 1a with metal for connecting metallic thin wires. In this device, the bonded portions of the inner leads 1a to the adhesive layer 2 are entirely coated with at least one kind of metal which is different from the metal plated to the parts of the inner leads 1a for connecting thin metal wires, and selected from among gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium, and zirconium or its alloy.
摘要翻译：要解决的问题：为了防止在半导体器件中由离子迁移引起的诸如漏电，短路等故障的发生。解决方案：通过使用具有散热器的引线框架组装半导体器件，该引线框架通过将由铜或铜合金构成的内部引线1a通过形成在散热器3的表面上的粘合剂层2和电镀层3结合到散热器3而构成具有用于连接金属细线的金属的内部引线1a的至少一部分。在该装置中，内引线1a与粘合剂层2的接合部分全部涂覆有至少一种不同于镀金的金属与用于连接薄金属线的内引线1a的部分的金属，并选择从金，铂，铱，铑，钯，钌，铟，锡，钼，钨，镓，锌，铬，铌，钽，钛和锆或其合金中选择。

4. 发明专利

JP2004140398A Method of manufacturing resin-sealed semiconductor device 有权
公开(公告)号：JP2004140398A
公开(公告)日：2004-05-13
申请号：JP2003426015
申请日：2003-12-24
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： MIYAKI YOSHINORI , SUZUKI HIROMICHI , SUZUKI KAZUNARI , NISHIDA TAKAFUMI , ITO FUJIO , TSUBOSAKI KUNIHIRO , KAMEOKA AKIHIKO , NISHI KUNIHIKO
IPC分类号： H01L21/56
CPC分类号： H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/01015 , H01L2924/01047 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of enhancing the production yield of a resin-sealed semiconductor device. SOLUTION: The method of manufacturing a resin-sealed semiconductor device to be provided is to form a die pad such that the area of the main surface on which a semiconductor chip is mounted is smaller than the area of the semiconductor chip and to seal the semiconductor chip and the die pad into a resin-sealed body. The semiconductor chip and the die pad are arranged in a cavity of a metal mold such that the gap between the rear face of the die pad and the inner wall face, which faces the former, of the cavity is narrower than the gap between the main surface of the semiconductor chip and the inner wall face, which faces the former, of the cavity by the thickness of the die pad. Since the resin is injected from a center gate simultaneously into the upper and the lower sides of the cavity to form the resin-sealed body, there is no possibility that the semiconductor chip is pushed upward by the resin filled in the filling region in the rear side of the semiconductor chip. As a result, the failure that the semiconductor chip, bonding wires, and the like are exposed outside the resin-sealed body is prevented, and the yield of the resin-sealed semiconductor device can be enhanced. COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2003332513A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003332513A
公开(公告)日：2003-11-21
申请号：JP2002134952
申请日：2002-05-10
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO FUJIO , SUZUKI HIROMICHI
IPC分类号： H01L23/50 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495 , H01L23/52 , H01L23/544
CPC分类号： H01L21/561 , H01L21/4828 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L23/49506 , H01L23/49548 , H01L23/544 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/85 , H01L24/97 , H01L2223/54473 , H01L2224/05554 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/78301 , H01L2224/78703 , H01L2224/85 , H01L2224/85181 , H01L2224/92247 , H01L2224/97 , H01L2924/014 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/3025 , H01L2924/00014 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve the mounting precision of a QFN (quad flat non-leaded package) having external connection terminals on the rear of a package. SOLUTION: In a sealed body 3 of the QFN 1, notches 8 are formed in two corners along the diagonal line direction of the surface side of the sealed body. A recognition mark 15 having a circular plate form is formed in a part of a suspension led 5b exposed from the notch 8. When the QFN 1 is mounted on a wiring board, the recognition mark 15 can be optically detected from above the sealed member 3. The recognition mark 15 is formed by removing a part of a metal plate constituting the suspension lead 5b by etching or by punching the part by a pressing machine. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提高在封装背面具有外部连接端子的QFN（四边形扁平无铅封装）的安装精度。解决方案：在QFN1的密封体3中，沿着密封体的表面侧的对角线方向的两个角部形成有切口8。在从凹口8露出的悬架引线5b的一部分上形成具有圆板形状的识别标记15.当QFN1安装在布线板上时，可以从密封构件3的上方光学检测识别标记15 通过蚀刻或通过冲压机冲压该零件来除去构成悬挂引线5b的金属板的一部分来形成识别标记15。版权所有（C）2004，JPO

6. 发明专利

JP2004048023A Method for manufacturing lead frame 有权
公开(公告)号：JP2004048023A
公开(公告)日：2004-02-12
申请号：JP2003207141
申请日：2003-08-11
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： KAJIWARA YUJIRO , SUZUKI KAZUNARI , TSUBOSAKI KUNIHIRO , SUZUKI HIROMICHI , MIYAKI YOSHINORI , NAITO TAKAHIRO , KAWAI SUEO
IPC分类号： H01L23/50 , H01L21/48 , H01L21/52 , H01L21/60 , H01L23/495
CPC分类号： H01L24/743 , H01L21/4842 , H01L23/49503 , H01L23/49513 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/02166 , H01L2224/29007 , H01L2224/2919 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/743 , H01L2224/82181 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/85181 , H01L2224/859 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , Y10T29/49121 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To improve a reflow crack resistance of a large-scale integrated circuit package, and to provide a method for manufacturing a lead frame suitable to manufacture a small quantity multiple-kind large-scale integrated circuit package. SOLUTION: A method for manufacturing the lead frame includes a step of preparing a die pad 3 (chip-placing part) which can place a semiconductor chip 2 of a different profile size, a plurality of inner leads parts 5a, disposed so as to surround the pad 3 and having a cuttable region, and the frame 1 having a hanging lead 4 connected to the pad 3, and a step of cutting the cuttable region of the lead parts 5a in a required length in response to a profile size of the chip 2 connected to the pad. COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2004014823A Semiconductor device and its fabricating method 审中-公开
公开(公告)号：JP2004014823A
公开(公告)日：2004-01-15
申请号：JP2002166549
申请日：2002-06-07
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO FUJIO , SUZUKI HIROMICHI
IPC分类号： H01L23/48 , H01L21/56 , H01L21/68 , H01L23/31 , H01L23/495 , H01L23/50 , H01L25/10
CPC分类号： H01L23/49551 , H01L21/565 , H01L21/566 , H01L23/3107 , H01L23/4951 , H01L23/49575 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/06136 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48624 , H01L2224/48647 , H01L2224/73215 , H01L2224/73265 , H01L2224/83192 , H01L2224/92147 , H01L2224/97 , H01L2225/1029 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/3511 , H01L2224/85 , H01L2924/00014 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve the process yield of a semiconductor device suitable for multiple pins. SOLUTION: The semiconductor device includes semiconductor chips arranged with a plurality of electrodes in their main surface, a plurality of leads each coupled electrically to a plurality of the electrodes of the semiconductor chips, and a resin sealant for sealing the semiconductor chips and a plurality of the leads, which include first leads that is exposed from a mounting surface of the resin sealant and have first external coupling portions positioned in a side surface of the resin sealant and second leads that are adjacent to the first leads and are exposed from the mounting surface of the resin sealant sealing and are besides provided with second external coupling portions positioned nearer to a side of the semiconductor chips than the first external coupling portions. The first and second leads are adhered and fixed to the semiconductor chips. COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2004319773A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2004319773A
公开(公告)日：2004-11-11
申请号：JP2003111838
申请日：2003-04-16
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO FUJIO , SUZUKI HIROMICHI
IPC分类号： H01L21/02
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for improving the working rate of a line.
SOLUTION: A lead frame in which a plurality of device areas are sectioned and formed and a recognizable mark is attached to the respective device areas is prepared, and two or more kinds of semiconductor chips are successively loaded corresponding to the device areas of the lead frame on the basis of an assembly condition by the recognizable mark. By managing the information of the recognizable mark in a computer 3 and instructing the assembly condition based on the information of the recognizable mark in the respective assembly processes of the same assembly line by the computer 3, successive assembly is executed to the two or more kinds of the semiconductor chips on the lead frame. The two or more kinds of the semiconductor devices are assembled from the same lead frame, and the working rate of the line is improved in products of many kinds in small quantities.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种用于提高线路工作速度的半导体器件的制造方法。解决方案：制备其中多个器件区域被分割并形成并且可识别标记附着到各个器件区域的引线框架，并且对应于器件区域的器件区域依次加载两种或更多种半导体芯片基于可识别标记的装配条件的引线框架。通过在计算机3中管理可识别标记的信息，并且基于计算机3在相同组装线的相应组装过程中基于可识别标记的信息指示组装条件，对两种或更多种类型进行连续组装的引线框架上的半导体芯片。两种以上的半导体器件由相同的引线框架组装，并且线路的工作速率在许多种类的少量产品中得到改善。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004214233A Semiconductor device and manufacturing method therefor 审中-公开
公开(公告)号：JP2004214233A
公开(公告)日：2004-07-29
申请号：JP2002378625
申请日：2002-12-26
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO FUJIO , SUZUKI HIROMICHI , TAKENO HIROYUKI , SHIMOJI HIROSHI , MURAKAMI FUMIO , KURAKAWA KEIKO
IPC分类号： H01L23/28 , H01L21/56 , H01L23/495 , H01L23/50
CPC分类号： H01L24/97 , H01L21/565 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/78301 , H01L2224/85181 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01055 , H01L2924/01056 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve manufacturing yield of QFN (Quad Flat Non-leaded package) and to promote multiple pins. SOLUTION: A resin sealing body 3 sealing a semiconductor chip 2 is formed. A peripheral part of the resin sealing body 3 and a lead frame LF 1 are cut along a cut line C positioned on an inner side (center side of the resin sealing body 3) rather than a line (mold line) along an outer edge of the resin sealing body 3. Thus, a whole periphery (upper face, lower face and both sides) of a lead 5 exposed to a side (cut face) of the resin sealing body 3 is covered by resin. Consequently, metallic burrs do not occur in the cut face of the lead 5. COPYRIGHT: (C)2004,JPO&NCIPI

10. 发明专利

JP2005101669A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005101669A
公开(公告)日：2005-04-14
申请号：JP2005004077
申请日：2005-01-11
申请人： Hitachi Ulsi Systems Co Ltd , Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO FUJIO , TANAKA HIROAKI , SUZUKI HIROMICHI , TOIDA TOKUJI , KONNO TAKASHI , TSUBOSAKI KUNIHIRO , TANAKA SHIGEKI , SUZUKI KAZUNARI , KAMEOKA AKIHIKO
IPC分类号： H01L23/50
CPC分类号： H01L2224/05554 , H01L2224/32245 , H01L2224/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To stabilize the bonding of a narrow lead pitch and prevent the package crack of a semiconductor device provided with a heatsink. SOLUTION: In a semiconductor device provided with a heatsink, the lead width w and the lead plate thickness t of the tip end of an inner lead connected to a semiconductor chip is set to be w COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了稳定窄引线间距的接合，并防止设置有散热片的半导体器件的封装裂纹。解决方案：在具有散热器的半导体器件中，连接到半导体芯片的内引线的前端的引线宽度w和引线板厚度t设定为w

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