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1. 发明专利

JP2004030488A Method for providing service 审中-公开
公开(公告)号：JP2004030488A
公开(公告)日：2004-01-29
申请号：JP2002188936
申请日：2002-06-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： IMAI HIROAKI , YOSHIZAWA KAZUO , SUZUKI TAKESHI
IPC分类号： G06Q50/10 , G06F15/00 , G06Q10/00 , G06Q30/02 , G06Q30/06 , G06Q50/00 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To realize secure service providing by connecting a service provider and a user. SOLUTION: The user who can use the Internet registers his/her own information in an agent. An Internet service provider (ISP) registers service information provided by the ISP itself. The agent stores information about both the user and the ISP's information, recognizes requests from the both sides on the basis of the information, further authenticates them, thereby connecting the ISP and the user and providing a service through the Internet by authenticating them. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2005260431A Communication charge charging method and system, and portable storage medium 审中-公开
标题翻译：通信充电收费方法与系统及便携式存储媒体
公开(公告)号：JP2005260431A
公开(公告)日：2005-09-22
申请号：JP2004067093
申请日：2004-03-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： IMAI HIROAKI , YOSHIZAWA KAZUO , SHIRATORI TADASHI
IPC分类号： H04M3/42 , H04M15/12
摘要： PROBLEM TO BE SOLVED: To sort communication charge accurately depending on private use and public use using one communication terminal.
SOLUTION: The method for charging communication charge of a communication terminal being used by a user depending on private use and public use comprises: a step for transmitting a public flag indicating public use to a charging server acquiring the communication log of a communication terminal so that the communication rate is charged to the communication terminal connected with a portable storage medium being provided to the user from the side paying the communication rate incident to public use; and a public communication log recording step where the charging server receiving the public flag stores the communication log in a communication log data base in correspondence with the public flag.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：使用一个通信终端，根据私人使用和公共使用来精确地分类通信费用。解决方案：根据私人使用和公共使用，由用户使用的通信终端的通信费用计费方法包括：将指示公共使用的公共标志发送到获取通信的通信日志的计费服务器的步骤终端，使得通信速率从支付公共使用的通信速率的一方向与用户提供的便携式存储介质连接的通信终端充电; 以及公共通信日志记录步骤，其中接收公共标志的计费服务器将通信日志存储在与公共标志相对应的通信日志数据库中。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JPH07271834A LOGIC SIMULATION SYSTEM 失效
公开(公告)号：JPH07271834A
公开(公告)日：1995-10-20
申请号：JP6477294
申请日：1994-04-01
申请人： HITACHI LTD
发明人： ITO SEIRO , SHIKAWA HIDEO , CHICHII YASUHIRO , NANBA YASUNORI , KUROSAKI MASATO , YOSHIZAWA KAZUO
IPC分类号： G06F17/50
摘要： PURPOSE:To provide a logic simulation system capable of automatically generating a test program effective for the request controlling logic verification of a logic circuit to be tested and efficiently executing logic verification. CONSTITUTION:The logic simulation system is constituted of a test program 1, an operation parameter 2 for storing the address of a machine word instruction, a function specification regulating a data format, the memory constitution specification of a cache or the like built in a processor, and a request controlling operation specification issued from a certain processor, a request generating device 3 for analyzing whether a request is generated in a read machine word instruction group or not, stores a machine word instruction of which request generation is recognized and request information annexed to the instruction group in an input value parameter 31 and editing the stored contents as a request generating test program 32, a logic simulator 4 for preparing an expected value and verifying the logic of the logic circuit to be tested, and a comparing/judging device 5 for comparing an expected value parameter 51 with a result value 52 at the time of detecting abnormality in logic simulation and judging a position generating a defective factor.

4. 发明专利

JPH02222070A PICTURE PRODUCTION PROCESSING METHOD 失效
公开(公告)号：JPH02222070A
公开(公告)日：1990-09-04
申请号：JP4186589
申请日：1989-02-23
申请人： HITACHI LTD
发明人： NAKAJIMA TERUO , YOSHIZAWA KAZUO
IPC分类号： H05K3/00 , G06F17/50
摘要： PURPOSE:To recognize the piercing state of a hole at multi-layer simultaneous picture production by converting the data on a wiring pattern, etc. CONSTITUTION:A processor 2 converts a wiring pattern, the hole information, etc., into the data that can produce pictures. In this case, the names of layers forming a printed board are read out of a substrate information file 2 and sorted and set in the laminating order. Then the hole information is read out of a wiring information file 4 for production of a form, and the hole piercing layer names of the coordinates are set via the form. The laminating order is extracted as the layer name used as a key. The corresponding bit position of a piercing state store area is obtained from the laminating order. Then a bit train showing the hole piercing state of the relevant coordinates is obtained within the piercing state store area corresponding to each coordinates. The bit train is used for production of pictures so that the hole piercing state is known on a drawing as long as a corresponding pattern is decided.

5. 发明专利

JPS6428784A METHOD FOR WIRING PRINTED BOARD 失效
公开(公告)号：JPS6428784A
公开(公告)日：1989-01-31
申请号：JP18501687
申请日：1987-07-24
申请人： HITACHI LTD
发明人： NAKAJIMA TERUO , YOSHIZAWA KAZUO
IPC分类号： H05K3/00 , G06F17/50
摘要： PURPOSE:To eliminate a correction through the labor of a human being and to improve a wiring performance by setting an area frame impossible to wire for observing a wiring rule and searching a wiring path in an area possible to wire excluding this area frame. CONSTITUTION:In order to set the area frame impossible to wire, initially, a lattice point coordinate for limiting a tap length to a prescribed length is calculated. The coordinates of the lattice points are the lattice point coordinates of D and E. When a tap off length is defined to be (l) lattices from a distance 7, the coordinate of the D point is obtained from the coordinate of a lattice point B and (l), so that the coordinates of the points D and E are calculated and the frame area frame 11 impossible to wire is set according to the coordinates. The frame 11 is the area of + or -2 lattices in an (x) direction from a segment DE. Then, the area frame 11 is excluded from the area frame possible to wire to search the wiring path in the area frame possible to wire except the area frame impossible to wire to wire from a pin 2 to 3 along the path 12. Thereby, a wiring pattern exceeding the tap length cannot be formed nor the correction through the labor of the human being is required.

6. 发明专利

JPS5510649A MEMORY ACCESS SYSTEM 失效
公开(公告)号：JPS5510649A
公开(公告)日：1980-01-25
申请号：JP8301578
申请日：1978-07-10
申请人： HITACHI LTD
发明人： YOSHIZAWA KAZUO
IPC分类号： G06F9/22 , G06F9/34 , G06F12/06 , G06F13/00
摘要： PURPOSE:To make access to an extended control memory possible by minimizing alteration by providing a latch controlled by an operation decoding circuit, and by the latch and an address latch. CONSTITUTION:For access to extended control memory 7, latch 6 is set by operation decoding circuit 5. In a set mode, memory 7 is selected and in a reset mode, memory 3 is selected. Address latch 2 is shared by memories 3 and 7 and access to extended control memory 7 can be attained by latches 2 and 6. In this way, adding a new latch makes it possible to use a conventional access mechanism as it is and access becomes possible with its alteration minimized.

7. 发明专利

JPH08263451A TEST DATA GENERATOR AND LOGIC SIMULATION SYSTEM 失效
公开(公告)号：JPH08263451A
公开(公告)日：1996-10-11
申请号：JP6031595
申请日：1995-03-20
申请人： HITACHI LTD
发明人： NANBA YASUNORI , ITO SEIRO , SHIKAWA HIDEO , YOSHIZAWA KAZUO
IPC分类号： G06F11/22 , G06F11/25 , G06F15/16 , G06F17/50
摘要： PURPOSE: To efficiently verify a logic circuit to be tested for controlling respective memories by generating a request sequence, initial value and expected value and setting them to the memories while referring to an input data part and a simulation information register part. CONSTITUTION: The attached information register part of a simulation information register part 11 registers addresses, address parity error, line transfer, line back and the initial setting inhibition of those addresses, ROW numbers and memories as the attached information of processors and requests and similarly registers the attached information of request for each request of each processor. Besides, the memory constitution register part of the simulation information register part 11 registers an address range and capacity for each memory. Further, an input data part 12 defines the method of a test to the logic circuit to be tested. Then, a request generating part 13 generates a request sequence 2, initial value 3 and expected value 4 to be issued to the logic circuit to be tested according to the test method of input data while referring to the simulation information register part 11.

8. 发明专利

JPH02204868A CHECKING METHOD FOR MOUNTING DESIGN 失效
公开(公告)号：JPH02204868A
公开(公告)日：1990-08-14
申请号：JP2385689
申请日：1989-02-03
申请人： HITACHI LTD
发明人： YOSHIZAWA KAZUO
IPC分类号： H05K3/00 , G06F17/50
摘要： PURPOSE:To accurately detect the defects in an early stage of designing by performing a tentative wiring when the parts are mounted on a printed board to decide the presence or absence of an oblique wiring layer and an instruction given from a designer for the wiring length and supposing accurately the wiring length after wiring to check the mounting check. CONSTITUTION:A tentative wiring is carried out among the parts whose connecting order is already decided, and the presence or absence of an oblique wiring layer is decided. When the presence of the oblique wiring layer is confirmed, the presence or absence of an instruction is decided for application of the oblique wiring layer. If the presence of the instruction is confirmed, the smallest wiring length is calculated with use of the oblique wiring layer. When the absence of the instruction is confirmed, the smallest wiring length is calculated with use of an orthogonal wiring layer. Then the presence or absence of an instruction is decided for the wiring length. When the instruction is confirmed, the designated wiring length is compared with the calculated smallest wiring length. If the former length is larger than the latter one, this relation is applied to calculation of the wiring length. In the case no instruction is confirmed or the former wiring length is smaller than the latter one, the calculated smallest wiring length is used for calculation of the wiring length. Based on this wiring length, the mounting design check is carried out for the delay time of signal transmission, the load interval, the total wiring length. Thus it is possible to accurately detects the defects at an early stage of mounting.

9. 发明专利

JPS60173670A SEAT RESERVATION SYSTEM 失效
公开(公告)号：JPS60173670A
公开(公告)日：1985-09-07
申请号：JP2852584
申请日：1984-02-20
申请人： HITACHI LTD
发明人： YOSHIZAWA KAZUO
IPC分类号： G06Q30/06 , G06Q50/00 , G06F15/26
摘要： PURPOSE:To decrease the number of inquiries to a central system by assigning a seat to each seat terminal device in advance and handling only the seat assigned to each seat reservation terminal device in most cases. CONSTITUTION:When an inquiry of an idle seat comes from a seat reservation terminal device 8, a decentralized processing unit 6 retrieves a decentralized storage device 7 and when all the designated tickets for the assigned seats are sold out, then the decentralized processing unit 6 informs the sold-out to a central system 1 via a communication line 4 and gives a sales request of the seat designation ticket. The central system 1 uses the rest seats of other terminal system 5 stored in the storage device 3 at the central side and starts the job of seat reservation from the terminal system 5. When the other terminal systems 5 sold out the rest seats, the central system 1 gives a commond of transfer of the rest seats to the other systems 5 so as to compensate the seats.

10. 发明专利

JPS5365029A MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS5365029A
公开(公告)日：1978-06-10
申请号：JP14013076
申请日：1976-11-24
申请人： HITACHI LTD
发明人： YOSHIZAWA KAZUO
IPC分类号： G06F9/24 , G06F9/22 , G06F13/00 , G11C7/00
摘要： PURPOSE:To reduce the time required for the completion of MP execution, by executing the MP written in already at a vacant time caused at the written in time of the microprogram MP.

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