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1. 发明专利

JP2012256087A Data processing device and data processing method 审中-公开
标题翻译：数据处理设备和数据处理方法
公开(公告)号：JP2012256087A
公开(公告)日：2012-12-27
申请号：JP2009209644
申请日：2009-09-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KODAMA MASAYUKI , SAEN MAKOTO , ITO KIYOHITO
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： PROBLEM TO BE SOLVED: To solve such a problem in a packet communication based method applied to a data processing device performing large scale calculation by using a large capacity of a CPU, that granularity of transfer or overhead is large, and for reducing the granularity of transfer and overhead it requires costs for modifying the CPU and/or an OS.SOLUTION: A data processing device comprises: an initiator IP module; a request transfer circuit; a response transfer circuit; and two or more clusters including a self-cluster numbered register and the like. When there is access to a specific address in response to a request from the initiator IP module, the device is configured to give information necessary for transfer to another cluster and determine whether a transfer destination is its own cluster or the other cluster on the basis of the information to transfer data. For performing access from its own cluster to the other cluster, the device is configured to set a cluster number and an address of the transfer destination before accessing the other cluster.
摘要翻译：要解决的问题：为了解决应用于通过使用CPU的大容量进行大规模计算的数据处理装置的分组通信方法中的这种问题，传输粒度或开销大，并且为了减少转移的粒度和开销需要修改CPU和/或OS的成本。解决方案：数据处理设备包括：发起者IP模块; 请求传输电路; 响应传输电路; 以及包括自身簇编号寄存器等的两个或更多个簇。当响应于来自发起者IP模块的请求访问特定地址时，该设备被配置为向另一个集群提供传送所需的信息，并基于以下方式确定传输目的地是其自己的集群还是其他集群信息传输数据。为了执行从自己的集群到其他集群的访问，设备配置为在访问其他集群之前设置集群号和传输目的地的地址。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2010034436A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2010034436A
公开(公告)日：2010-02-12
申请号：JP2008197277
申请日：2008-07-31
申请人： Hitachi Ltd , Keio Gijuku , 学校法人慶應義塾 , 株式会社日立製作所
发明人： KURODA TADAHIRO , OSADA KENICHI , SAEN MAKOTO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/48091 , H01L2924/01055 , H01L2924/1305 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor circuit device which can achieve a stable operation with a small delay between chips in laminated chip layers. SOLUTION: Memory chips MEM_A and MEM_B are laminated on a logic chip LOG, and the transmission and reception of commands, addresses, data etc. between the chip LOG and the memory chips MEM_A and MEM_B are performed by wireless communication using inductive coupling transmission terminal groups 211, 214, 218 and 219, and inductive coupling reception terminal groups 212, 213, 215 to 217. A power source of the MEM_A and MEM_B is supplied by wire bonding elements 225 and 227, and a reset signal which initializes inner states of the MEM_A and MEM_B is supplied by wire bonding elements 222 and 224. By using the wireless communication, communication can be performed with a small delay even if operation voltages between the chips are different, and a stable operation can be achieved by supplying signals necessitating a power source or reliability by means of wired transmission. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体电路器件，其可以在层叠芯片层中的芯片之间以小的延迟实现稳定的操作。解决方案：存储器芯片MEM_A和MEM_B层叠在逻辑芯片LOG上，并且通过使用电感耦合的无线通信来执行芯片LOG与存储器芯片MEM_A和MEM_B之间的命令，地址，数据等的发送和接收传输端子组211,214,218和219，以及电感耦合接收端子组212,213,215至217。MEM_A和MEM_B的电源由引线键合元件225和227提供，并且将复位信号初始化为内部 MEM_A和MEM_B的状态由引线键合元件222和224提供。通过使用无线通信，即使芯片之间的操作电压不同，也可以以小的延迟进行通信，并且可以通过提供信号来实现稳定的操作通过有线传输需要电源或可靠性。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009032857A Semiconductor integrated circuit, and semiconductor device 审中-公开
标题翻译：半导体集成电路和半导体器件
公开(公告)号：JP2009032857A
公开(公告)日：2009-02-12
申请号：JP2007194313
申请日：2007-07-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NONOMURA ITARU , SAEN MAKOTO , OSADA KENICHI
IPC分类号： H01L21/822 , H01L27/04 , H04B5/02
CPC分类号： G06F13/4045 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an interconnect constructing technique capable of ensuring efficient access from an IP mounted on one semiconductor chip to an IP mounted on the other semiconductor chip by transmitting and receiving the packet between the chips through the interconnect built in the semiconductor chip by using a three-dimensional coupling technology. SOLUTION: A semiconductor integrated circuit includes: an initiator for transmitting an access request; a target for receiving the access request to transmit an access response; a router (a router A105) for relaying the access request and the access response; and the three-dimensional coupling circuit (a three-dimensional transmitting and receiving part A1301) for communicating with the outside. The three-dimensional coupling circuit is adjacently arranged to the router. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种互连构造技术，其能够通过在内置的互连件之间发送和接收芯片之间的分组，从而确保从安装在一个半导体芯片上的IP到安装在另一个半导体芯片上的IP的有效接入半导体芯片采用三维耦合技术。解决方案：半导体集成电路包括：用于发送访问请求的发起者; 用于接收所述访问请求以发送访问响应的目标; 路由器（路由器A105），用于中继接入请求和接入响应; 以及用于与外部通信的三维耦合电路（三维发送和接收部分A1301）。三维耦合电路相邻地布置在路由器上。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2013033999A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013033999A
公开(公告)日：2013-02-14
申请号：JP2012234820
申请日：2012-10-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAEN MAKOTO , OSADA KENICHI , YAMAOKA MASANAO , SEKIGUCHI TOMONORI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a laminated LSI which achieves communication of low latency and high throughput between LSIs.SOLUTION: A semiconductor device eliminates the need for an arbitration operation by adopting a connection topology for connecting a circuit (TR_00T) performing one transmission and circuits (TR_10R,TR_20R,TR_30R) performing a plurality of receptions with respect to one through electrode group (e.g., TSVGL_0). Specifically, a rewritable storage element for designating whether each through electrode port is used for transmission or for reception and designating address assignment of each through electrode port with respect to each laminated LSI is mounted for allowing the connection topology even when a plurality of same LSIs are laminated.
摘要翻译：要解决的问题：提供在LSI之间实现低延迟和高吞吐量的通信的层叠LSI。解决方案：半导体器件通过采用用于连接执行一个传输的电路（TR_00T）的连接拓扑和相对于一个通过电极执行多个接收的电路（TR_10R，TR_20R，TR_30R）而不需要仲裁操作组（例如，TSVGL_0）。具体地说，即使在多个相同的LSI是LSI的情况下，也安装了用于指定每个贯通电极端口是用于发送还是用于接收的可重写存储元件，并且为每个通过电极端口指定每个层叠LSI的地址分配，以允许连接拓扑层压。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2009266258A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009266258A
公开(公告)日：2009-11-12
申请号：JP2008110839
申请日：2008-04-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HANZAWA SATORU , KUME HITOSHI , TERAO MOTOYASU , SEKIGUCHI TOMONORI , SAEN MAKOTO
IPC分类号： G11C29/04 , G11C13/00 , G11C29/44 , H01L25/04 , H01L25/18 , H01L27/10 , H01L27/105
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable large capacity phase change memory module. SOLUTION: A semiconductor device includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and the current mirror circuit. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供高度可靠的大容量相变存储器模块。解决方案：半导体器件包括具有堆叠使用硫族化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且初始化条件和重写条件根据层所选择的存储单元被定位。根据操作选择电流镜电路，并且根据电压选择电路和电流镜中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件）电路。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2010080802A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010080802A
公开(公告)日：2010-04-08
申请号：JP2008249496
申请日：2008-09-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ITO KIYOHITO , SAEN MAKOTO , KURODA YUKI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , H01L23/544 , H01L23/552 , H01L25/0657 , H01L25/18 , H01L2223/54433 , H01L2223/5444 , H01L2223/54473 , H01L2224/05571 , H01L2224/16145 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06558 , H01L2924/00014 , H01L2924/01057 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： PROBLEM TO BE SOLVED: To solve the problem that the increase in parasitic capacitance and parasitic resistance of wiring for communication in a semiconductor device wherein a plurality of memory LSIs and a plurality of processor LSIs are laminated, results in the degradation in power and speed performance of an entire system because distances of data communication between memory LSIs and processor LSIs are increased in accordance with the increase in number of laminated LSIs. SOLUTION: At least two pairs of operation LSIs 100 and memory LSIs 200 are laminated, and the operation LSI 100 and the memory LSI 200 of each pair are laminated adjacently to each other in a perpendicular direction. Communication between the operation LSI 100 and the memory LSI 200 of each pair is performed through a dedicated electrode provided between them. Communication between operation LSIs 100 and communication from operation LSIs 100 to the outside are performed through a silicon through electrode 11 for signals piercing all LSIs. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了解决层叠多个存储器LSI和多个处理器LSI的半导体器件中的用于通信的布线的寄生电容和寄生电阻的增加的问题，导致功率的降低并且根据层叠LSI的数量的增加，存储器LSI和处理器LSI之间的数据通信距离增加，因此整个系统的速度性能。解决方案：层叠至少两对操作LSI 100和存储器LSI 200，并且每对的操作LSI 100和存储器LSI 200在垂直方向上彼此相邻地层叠。通过设置在它们之间的专用电极来执行每对操作LSI 100与存储器LSI 200之间的通信。通过用于穿透所有LSI的信号的硅通电极11执行操作LSI 100之间的通信和从操作LSI 100到外部的通信。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010080801A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010080801A
公开(公告)日：2010-04-08
申请号：JP2008249495
申请日：2008-09-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KURODA YUKI , SAEN MAKOTO , MIZUNO HIROYUKI , ITO KIYOHITO
IPC分类号： H01L25/065 , H01L21/822 , H01L25/07 , H01L25/18 , H01L27/04
CPC分类号： H01L25/18 , G11C5/02 , G11C5/04 , G11C29/02 , G11C29/025 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/3011 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To solve such a problem that while transfer between a processor LSI and a memory increases year by year to require improvement in communication amount and reduction of electric power needed for communication, methods of laminating LSIs to shorten communication distances are considered and reduction of the cost for laminating processes and expansion of the flexibility of memory LSIs to be laminated are needed for conventional simple lamination of the processor LSIs and memory LSIs. SOLUTION: High-speed, large-capacity communication is carried out through the shortest path by: laminating processor LSIs, including an external communication LSI having a circuit for high-speed communication exceeding 1 GHz with outside a laminate LSI, a general CPU, etc., and memory LSIs, including a DRAM etc., in this order; and connecting those LSIs by silicon penetration electrodes. Further, an interposer for facilitating connection with the processor LSIs is connected to input/output terminals of the laminated memory LSIs, thereby improving the flexibility of memory. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题为了解决在处理器LSI和存储器之间的转移逐年增加以要求通信量的改善和通信所需的电力的减少的问题，层叠LSI的方法来缩短通信距离对于处理器LSI和存储器LSI的常规简单层叠，需要层叠处理的成本降低和层叠的存储器LSI的灵活性的扩大。解决方案：通过以下方式，通过最短的路径进行高速，大容量的通信：将包括具有超过1GHz的高速通信用电路的外部通信LSI与层叠LSI外部层叠的处理器LSI组合在一起 CPU等，以及包括DRAM等的存储器LSI; 并通过硅穿透电极连接这些LSI。此外，用于便于与处理器LSI的连接的插入器连接到层叠存储器LSI的输入/输出端子，从而提高存储器的灵活性。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009026792A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009026792A
公开(公告)日：2009-02-05
申请号：JP2007185425
申请日：2007-07-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NONOMURA ITARU , OSADA KENICHI , SAEN MAKOTO
IPC分类号： H01L25/065 , H01L21/822 , H01L25/07 , H01L25/18 , H01L27/04
CPC分类号： H01L25/0657 , H01L23/48 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/0401 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/01075 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a technology for laminating a plurality of chips of the same design and increasing three-dimensional connection information transfer ability, by eliminating a spacer and an interposer in a semiconductor device. SOLUTION: A first semiconductor integrated circuit (SoC 301), comprising a three dimensional connection circuit (a three dimensional connection transmission terminal group and a three dimensional connection reception terminal group), a second semiconductor integrated circuit (memory A 302), comprising the three dimensional connection circuit and a through electrode (a power through via and a ground through via), and a third semiconductor integrated circuit (memory B 303), comprising the three dimensional connection circuit and the through electrode are laminated on a package substrate. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在半导体器件中消除间隔物和插入件来提供用于层叠相同设计的多个芯片并增加三维连接信息传递能力的技术。解决方案：包括三维连接电路（三维连接传输端子组和三维连接接收端子组）的第一半导体集成电路（SoC 301），第二半导体集成电路（存储器A 302）包括三维连接电路和贯通电极（通过通孔和通孔的通孔），以及包括三维连接电路和通孔的第三半导体集成电路（存储器B 303）层叠在封装基板。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2012152870A Manipulator device, and work device with manipulator 有权
标题翻译：操纵器装置和具有操纵器的工作装置
公开(公告)号：JP2012152870A
公开(公告)日：2012-08-16
申请号：JP2011015268
申请日：2011-01-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ITO KIYOHITO , SAEN MAKOTO
IPC分类号： B25J19/04 , H04N5/225
摘要： PROBLEM TO BE SOLVED: To acquire the information for operating a manipulator so that an object to be held at any position can come into a range in which the object can be held by the manipulator, and also present the information to an operator so as to be easily understood.SOLUTION: This manipulator device includes an arm part and a hand part. The hand part includes one or more finger parts for holding an object in a holdable range. A first omnidirectional imaging device is provided to the tip of the finger part, and a second omnidirectional imaging device is provided to the hand part at a position other than the tip of the finger part. The first omnidirectional imaging device and the second omnidirectional imaging device are configured so that the imaging axes thereof differ from each other, for example, cross each other. It can be determined that the object comes within the holdable range by confirming that the object is not projected on a picture imaged by the first omnidirectional imaging device and the object is not projected on a picture imaged by the second omnidirectional imaging device.
摘要翻译：要解决的问题：获取操作操纵器的信息，使得要保持在任何位置的物体可以进入物体可被操纵器保持的范围内，并且还将信息呈现给操作者以便容易理解。解决方案：该机械手装置包括臂部和手部。手部包括用于将物体保持在可保持范围内的一个或多个手指部分。第一全向成像装置被提供到手指部分的尖端，并且第二全向成像装置在除手指部分的尖端之外的位置处提供到手部分。第一全向成像装置和第二全向成像装置被配置成使得其成像轴彼此不同，例如彼此交叉。可以通过确认物体不投影在由第一全向成像装置成像的图像上并且物体不投射在由第二全向成像装置成像的图像上，可以确定物体在可保持的范围内。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2010177222A Wiring board and method of manufacturing the same 审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：JP2010177222A
公开(公告)日：2010-08-12
申请号：JP2009014883
申请日：2009-01-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMAGUCHI YOSHIHIDE , MATSUSHIMA NAOKI , SAEN MAKOTO , NISHIJIMA NORIYO , AONO TAKANORI
IPC分类号： H01L23/12 , H01L23/34 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide an interposer substrate for a mounting structure that strikes a balance between an issue of shortening of electrical connection between semiconductor devices and an issue of thermal conduction between the semiconductor devices, relating to a semiconductor stacking implementation structure where semiconductor devices are stacked in multiple stages, and to provide a method of manufacturing the same. SOLUTION: In the semiconductor stacking implementation structure where semiconductor devices are stacked in multiple stages, a specific material 1 having an anisotropic heat dissipation is applied as a substrate for constituting a wiring board 13 for connecting semiconductor devices. Then, wiring layers 6, 8, and 9 as well as insulating layers 3 and 7 are formed on both sides of the anisotropic heat dissipation substrate, thereby striking a balance between the issues of shortening of electrical connection between semiconductor devices and of thermal shielding between semiconductor devices. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于在缩短半导体器件之间的电连接的问题和半导体器件之间的热传导问题之间的平衡的安装结构的内插器衬底，涉及半导体堆叠实施结构其中半导体器件以多级堆叠，并提供其制造方法。解决方案：在半导体器件以多级堆叠的半导体堆叠实施结构中，施加具有各向异性散热的特定材料1作为用于构成用于连接半导体器件的布线板13的基板。然后，在各向异性散热基板的两侧形成布线层6,8,9以及绝缘层3和7，从而在缩短半导体器件之间的电连接和缩短半导体器件之间的热屏蔽的问题之间取得平衡半导体器件。版权所有（C）2010，JPO＆INPIT

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