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1. 发明专利

JP2006201805A Computer system and display device 有权
标题翻译：计算机系统和显示设备
公开(公告)号：JP2006201805A
公开(公告)日：2006-08-03
申请号：JP2006066904
申请日：2006-03-13
申请人： Hitachi Advanced Digital Inc , Hitachi Ltd , 株式会社日立アドバンストデジタル , 株式会社日立製作所
发明人： FURUHASHI TSUTOMU , MAEDA TAKESHI , HIGA ATSUHIRO , OHARA TOSHIYUKI , KURIHARA HIROSHI , KASAI SHIGEHIKO
IPC分类号： G09G5/00 , G09G3/20 , G09G3/36 , G09G5/36 , G09G5/391
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display controller unit with which enlarged display is enabled even with a low-speed and low-capacity memory.
SOLUTION: If a video signal 105 is below middle resolution, enlargement processing is performed by a frame memory 110, a line memory 111, and an enlargement processing control circuit 118. When the input and output to the frame memory 110 are synchronized, the capacity of the frame memory 110 for two line components is sufficient. In the case where the video signal 105 is of the same high resolution as that of a liquid crystal display panel 124, the video signal105 (117) is outputted to a display timing generation circuit 120 through a gate circuit 109 and is displayed in a through mode. The processing by the frame memory 110 etc., is not performed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供即使在低速和低容量存储器下也能够进行放大显示的液晶显示控制器单元。解决方案：如果视频信号105低于中分辨率，则由帧存储器110，行存储器111和放大处理控制电路118进行放大处理。当帧存储器110的输入和输出被同步时两帧线路分量的帧存储器110的容量就足够了。在视频信号105具有与液晶显示面板124相同的高分辨率的情况下，视频信号105（117）通过门电路109输出到显示定时发生电路120，并以直通方式模式。不执行帧存储器110等的处理。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2004287454A Computer system and display device 有权
公开(公告)号：JP2004287454A
公开(公告)日：2004-10-14
申请号：JP2004139308
申请日：2004-05-10
申请人： Hitachi Advanced Digital Inc , Hitachi Ltd , 株式会社日立アドバンストデジタル , 株式会社日立製作所
发明人： FURUHASHI TSUTOMU , MAEDA TAKESHI , HIGA ATSUHIRO , OHARA TOSHIYUKI , KURIHARA HIROSHI , KASAI SHIGEHIKO
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00 , G09G5/36
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display controller capable of realizing an enlargement display even with a low-speed and low-capacity memory.
SOLUTION: When a video signal 105 has resolution below intermediate resolution, enlargement processing is carried out through a frame memory 110, a line memory 111, and an enlargement processing control circuit 118. The frame memory 110 needs to have only two-line capacity by synchronizing input to and output from the frame memory 110 with each other. When the video signal 105 has the same high resolution with a liquid crystal display panel 124, the video signal 105 (117) is outputted to a display timing generating circuit 120 through a gate circuit 109 and displayed in a through mode. Processing by the frame memory 110 etc. is not performed.
COPYRIGHT: (C)2005,JPO&NCIPI

3. 发明专利

JP2004350328A Tuner part, monitor part, and video and audio reproducing apparatus 有权
标题翻译：调谐器部件，监视器部件以及视频和音频再现装置
公开(公告)号：JP2004350328A
公开(公告)日：2004-12-09
申请号：JP2004249428
申请日：2004-08-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SOMEYA RYUICHI , ARAI IKUYA , SUGIYAMA MASAHITO , OHARA TOSHIYUKI
IPC分类号： H04B1/06 , H04B1/16 , H04N5/44 , H04N5/445
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal television easy to use without impairing installation or interior by laying round an antenna wire. SOLUTION: In a television receiver, the tuner part and the monitor part are separated, video and audio signals are transmitted from the tuner part to the monitor part, and control data are exchanged between the tuner part and the monitor part to eliminate the deviation of both operating states. Thus, the antenna wire is connected to the separated tuner part for tuning, and tuned video and audio signals are transmitted to the monitor part in a wireless manner to reproduce the video and audio signals. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了使液晶电视容易使用，而不会通过放置天线线而不损害安装或内部。解决方案：在电视接收机中，调谐器部分和监视器部分被分离，视频和音频信号从调谐器部分发送到监视器部分，并且在调谐器部分和监视器部分之间交换控制数据以消除两种运行状态的偏差。因此，天线被连接到分离的调谐器部分用于调谐，并且调谐的视频和音频信号以无线方式被发送到监视器部分以再现视频和音频信号。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2000338923A IMAGE DISPLAY DEVICE 失效
公开(公告)号：JP2000338923A
公开(公告)日：2000-12-08
申请号：JP15113899
申请日：1999-05-31
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MORI MASASHI , OHARA TOSHIYUKI , NISHITANI SHIGEYUKI , HIRUTA YUKIO , WATANABE AKIHIRO
IPC分类号： G09G3/36 , G09G3/20 , G09G3/296 , G09G3/28
摘要： PROBLEM TO BE SOLVED: To provide an image display device wherein jitters are smaller and flickerings are fewer. SOLUTION: A resolution detecting circuit 18 detecting a display mode from horizontal and vertical synchronizing signals and a DAC control circuit 23 are provided, and by making a VCO circuit 21 of a PLL circuit 15 generating a dot clock from the synchronizing signals into a constitution adding current values of a voltage-to-current conversion 46 and a current DAC circuit 31 and inputting it into a current-controlled oscillator 47, an output frequency range of the VCO circuit 21 is selected in accordance with the display mode for reducing a VCO circuit gain. Thereby, a device having smaller jitters and fewer flickerings is provided even in a crystal liquid display device supporting a display mode of high dot clock frequency.

5. 发明专利

JP2000010519A IMAGE DISPLAY DEVICE AND ITS SYSTEM 失效
公开(公告)号：JP2000010519A
公开(公告)日：2000-01-14
申请号：JP17238898
申请日：1998-06-19
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MORI MASASHI , NISHITANI SHIGEYUKI , MORI TATSUMI , KURIHARA HIROSHI , OHASHI TOSHIAKI , KASAI SHIGEHIKO , HIRUTA YUKIO , OHARA TOSHIYUKI
IPC分类号： G09G3/36 , G09G3/20
摘要： PROBLEM TO BE SOLVED: To correct a display brightness characteristic without deterioration in image quality by constituting a conversion means for converting an analog video signal into a digital video signal of an analog-to-digital converting means whose input/output characteristic has the corresponding characteristic to a correction target of a display brightness characteristic of the image display means. SOLUTION: An inputted analog signal 301 is converted into a digital video signal 333 by an analog-to-digital converting circuit 1 synchronizing with a clock 332 generated by a timing signal generating circuit 6. Here, the analog-to- digital converting circuit 1 is constituted to have such a characteristic that the input/output characteristic corresponds to the correction target of the display brightness characteristic of an image display module 8. Namely, a voltage regulating circuit 2 produces comparison voltage of the value corresponding to each of plural gradations and also corresponding to the correction target of the display brightness characteristic of the image display module 8. And an encoder 5 converts the comparison result obtd. by comparing the analog video signal voltage with the comparison voltage corresponding to each gradation into the digital video signal 333.

6. 发明专利

JPH09152848A LIQUID CRYSTAL DISPLAY CONTROLLER 失效
公开(公告)号：JPH09152848A
公开(公告)日：1997-06-10
申请号：JP31248395
申请日：1995-11-30
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： FURUHASHI TSUTOMU , MAEDA TAKESHI , HIGA ATSUHIRO , OHARA TOSHIYUKI , KURIHARA HIROSHI , KASAI SHIGEHIKO
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display controller capable of expanding a display only by a memory of a low speed and small-capacity. SOLUTION: When a resolution of a video signal 105 is below a medium degree, an expansion processing is performed by a frame memory 110, a line memory 111, and an expansion processing control circuit 118. When an input and an output to and from the frame memory 110 are synchronized, only a capacity of two lines suffices that of the frame memory 110. When video signal 105 has the same high resolution as a liquid crystal display panel 124, the video signal 105(117) is outputted to a display timing generation circuit 120 through a gate circuit 109 and is displayed in a through mode. No processing is performed by the frame memory 110, etc.

7. 发明专利

JP2001147667A LIQUID CRYSTAL MONITOR DEVICE 失效
公开(公告)号：JP2001147667A
公开(公告)日：2001-05-29
申请号：JP32775799
申请日：1999-11-18
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST , HITACHI MICRO SOFTWARE SYST
发明人： NISHITANI SHIGEYUKI , OHARA TOSHIYUKI , KASAI SHIGEHIKO , MAEDA TAKESHI , TAKAGI TETSUO
IPC分类号： G02F1/133 , G09F9/00 , G09F9/35 , G09G3/20 , G09G3/36 , H04N5/66 , H04N9/69
摘要： PROBLEM TO BE SOLVED: To solve such problem that, though the brightness, the tint, and gradation characteristics of liquid crystal are determined by characteristics of liquid crystal itself and a back light but they are diffused and this variance in brightness, tint, and gradation characteristics appear as unevenness of display to cause degradation of the quality especially in a multi-display device using plural liquid crystals. SOLUTION: A back light controller which adjusts the brightness of the back light of a liquid crystal display device on the basis of the measured result of luminance characteristics, color characteristics, and gradation characteristics of the liquid crystal display device and a data conversion circuit which corrects color display data on the basis of the measured result to output the correction result to the liquid crystal display device are provided to solve such problem.

8. 发明专利

JPH07262003A REGISTER ACCESS CONTROLLER 失效
公开(公告)号：JPH07262003A
公开(公告)日：1995-10-13
申请号：JP4835294
申请日：1994-03-18
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： JINUSHI MASAHIRO , FUKUDA TAKEHIRO , HAYASHI SHUICHI , OHARA TOSHIYUKI
IPC分类号： G06F7/00 , G06F9/34
摘要： PURPOSE:To change the mapping of a data register without changing any driver software by converting an index value outputted from the driver software into any other value and setting it to an index register. CONSTITUTION:The index value, which is outputted by the driver software, on a data bus 30 is stored in an index register 20. That stored index value 201 is converted into the other value and outputted through a selector 330 to a data bus 3. That value is set at one of a data register group 1 to be selected by a value set to an index register 2. Thus, the mapping of the data register can be changed without changing any driver software.

9. 发明专利

JPH08221157A INFORMATION PROCESSOR 失效
公开(公告)号：JPH08221157A
公开(公告)日：1996-08-30
申请号：JP2665795
申请日：1995-02-15
申请人： HITACHI LTD
发明人： MORIMOTO TAKUYA , OHARA TOSHIYUKI , AMANO OSAMU , MIZUTANI KOJI , NAGASAWA HIDEYUKI
IPC分类号： G06F1/26 , G06F3/00
摘要： PURPOSE: To provide an information processor which has a simplified interface between a power unit and a system device. CONSTITUTION: The information processor 1 has the power unit 2 which converts an alternating current supplied from a power source into a direct current, an output line 60 which is connected to the power unit 2, and the system device 3 which receives the direct current through the output line 60. The system device 3 is provided with a secondary battery 33 which is charged with the direct current. The power unit 2 has a switching circuit 26 which controls whether or not the direct current is outputted to the output line 60 according to a given instruction and a control circuit 22 which communicates with the system device 3 by using the output line 60 when the direct current is not outputted to the output line 60. The system device 3 has a CPU part 30 which is supplied with electric power from the secondary battery 33 and communicates with the power unit 2 by using the output line 60 when the direct current is not outputted to the output line 60.

10. 发明专利

JP2000003152A IMAGE DISPLAY DEVICE 失效
公开(公告)号：JP2000003152A
公开(公告)日：2000-01-07
申请号：JP16877298
申请日：1998-06-16
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MORI MASASHI , MORI TATSUMI , NISHITANI SHIGEYUKI , KURIHARA HIROSHI , HIRUTA YUKIO , OHARA TOSHIYUKI
IPC分类号： G09G3/36 , G09G3/20 , G09G5/00
摘要： PROBLEM TO BE SOLVED: To make it possible to suppress the oozing of colors even when an analog video signal has a skew between the respective colors by making it possible to regulate the phase of the analog video signal or the phase of a dot clock by colors. SOLUTION: A PLL circuit 15 forms the dot clock 109 synchronized with the edge of a horizontal synchronizing signal 104 by multiplying the horizontal synchronizing signal 104. The dot clock 109 is further discretely subjected to delay regulation by variable delay circuits 16 to 18 and is then outputted as conversion clocks 111 to 113, which are respectively the conversion timings to AD circuits 10 to 12. The AD circuits 10 to 12 convert the analog signals 101 to 103 respectively in synchronization with the conversion clocks 111 to 113 to digital video data 106 to 109 and output the data. As for the delay quantities of the variable delay circuit 16 to 18, a control circuit 20 changes the values of regulation signals 114 to 116 by colors in accordance with the operation result of a regulation switch circuit 19, thereby discretely regulating the delay quantities of the variable delay circuits 16 to 18 by colors.

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