专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2009198343A Detector arrangement substrate and nuclear medicine diagnosis device using it 审中-公开
标题翻译：检测器布置基板和使用它的核医学诊断设备
公开(公告)号：JP2009198343A
公开(公告)日：2009-09-03
申请号：JP2008040853
申请日：2008-02-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YANAGIDA NORIFUMI , KIYONO TOMOYUKI , ISHIZU TAKAAKI , IMAI TSUTOMU , KAWADA ATSUMI , KOMINAMI SHINYA
IPC分类号： G01T1/161 , G01T1/24
CPC分类号： G01T1/249 , G01T1/242 , G01T1/243
摘要： PROBLEM TO BE SOLVED: To provide a detector arrangement substrate capable of improving detection sensitivity and space resolution, and a nuclear medicine diagnosis device using it. SOLUTION: This detector arrangement substrate 30 is equipped with flat detection modules 40 formed respectively by piling a plurality of detection elements 50 having respectively a signal electrode 52 connected respectively to each detector in order to form a plurality of detectors for detecting a radiation, for reading out signals from each detector, and a bias electrode 53 for applying a bias voltage to each detector. On the XZ-plane for detecting the radiation, the detection modules 40 having respectively the plurality of detectors are arranged in the X-direction, and the detection modules 40 are arranged in a flat structure on both planes or on one plane of a wiring substrate 32 in the Z-direction, to thereby laminate detectors, and the plurality of detection modules 40 are provided in the Y-direction. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够提高检测灵敏度和空间分辨率的检测器布置基板，以及使用该检测器布置基板的核医学诊断装置。解决方案：该检测器布置基板30配备有分别通过堆叠多个检测元件50的平坦检测模块40，多个检测元件50分别具有分别连接到每个检测器的信号电极52，以便形成用于检测辐射的多个检测器，用于从每个检测器读出信号;以及偏置电极53，用于向每个检测器施加偏置电压。在用于检测辐射的XZ平面上，分别具有多个检测器的检测模块40沿X方向排列，并且检测模块40在布线基板的两个平面或一个平面上布置成平面结构 32，从而层叠检测器，并且将多个检测模块40设置在Y方向上。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009032999A Printed circuit board 有权
标题翻译：印刷电路板
公开(公告)号：JP2009032999A
公开(公告)日：2009-02-12
申请号：JP2007196882
申请日：2007-07-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OTANI KENGO , TAKAHIRA MITSURU , KAWADA ATSUMI , ONO TAKAYUKI
IPC分类号： H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a printed circuit board capable of avoiding the deterioration of reliability because of generation of short-circuit or migration in the pattern region of a component mounting unit.
SOLUTION: A method wherein the pattern region of the component mounting portion is separated from the pattern region of a substrate end part or a pattern is not arranged on the substrate end part is adopted.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够避免由于在部件安装单元的图案区域中产生短路或迁移而导致的可靠性劣化的印刷电路板。采用这样一种方法，其中组件安装部分的图案区域与衬底端部的图案区域或图案分离，不在衬底端部上。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2006269456A Mulitlayer printed wiring board and manufacturing method thereof 审中-公开
标题翻译：多层印刷接线板及其制造方法
公开(公告)号：JP2006269456A
公开(公告)日：2006-10-05
申请号：JP2005080919
申请日：2005-03-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TSUNODA ATSUSHI , ONO TAKAYUKI , KAWADA ATSUMI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To obtain a highly dense multilayer printed wiring board by reducing complication of processes and cost raise due to increases in times of perforation and plating, and stabilizing interlayer alignment accuracy in a sequential laminate method.
SOLUTION: Pins 30, 31 are formed on vias 10, 12 of a sub-assembly wiring board 1. These pins 30, 31 are inserted into vias 11, 13 of an opposing sub-assembly 2, and the pins are positioned, and thus, a substrate excellent in interlayer alignment accuracy of the sub-assembly wiring boards 1, 2 can be manufactured. The use of a material excellent in electric conductivity for the pins can electrically connect the two pairs of vias 10, 11 and 12, 13 which oppose each other. Also, the pins can improve hermetical performance and change thermal conductivity of the substrate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了通过减少由于穿孔和电镀时间的增加而减少工艺的复杂性和成本提高而获得高度致密的多层印刷线路板，并且在顺序层压方法中稳定层间对准精度。
解决方案：销子30,31形成在子组件布线板1的通孔10,12上。这些销30,31插入到相对的子组件2的通孔11,13中，并且销定位因此，可以制造出分组合布线板1,2的层间取向精度优异的基板。使用导电性优异的材料可以电连接彼此相对的两对通孔10,11和12,13。此外，销可以改善衬底的密封性能并改变衬底的导热性。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2010232237A Structure for mounting electronic device 有权
标题翻译：安装电子设备的结构
公开(公告)号：JP2010232237A
公开(公告)日：2010-10-14
申请号：JP2009075373
申请日：2009-03-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SEGUCHI KAZUHIRO , TAKAHIRA MITSURU , SHIMOIRISA TAKAHIRO , KIMURA SHOTARO , KAWADA ATSUMI , UCHIYAMA SHUICHI , NEHO YASUSHI
IPC分类号： H05K1/18
摘要： PROBLEM TO BE SOLVED: To solve the problem that, in the structure for mounting an electronic device, in the structure which uses a relay substrate, due to the use of connectors or the like on one surface of the relay substrate depending on the shapes of a module type connected thereto, a physical region on which nothing can be mounted exists on a back surface side thereof, and when the height of the module becomes taller than a connector for connection, physical regions increase by only the space thereof, and the size of the relay substrate become correspondingly larger as these physical regions increase, so that the size of the electronic device becomes large.
SOLUTION: In the structure for mounting an electronic device including a plurality of power supply units for supplying electric power to respective logic modules through the relay substrate while a plurality of modules are connected through a plurality of connectors provided on the relay substrate, the relay substrate and the plurality of power supply units are connected by a power source connection substrate provided with a plurality of power supply tabs for connection with the relay substrate and a plurality of connectors for connection with the plurality of power supply units.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题为了解决在用于安装电子设备的结构中，在使用继电器基板的结构中，由于在继电器基板的一个表面上使用连接器等而取决于连接到其上的模块类型的形状，在其背面侧上不存在任何物体的物理区域，并且当模块的高度变得比用于连接的连接器高时，物理区域仅增加其空间，并且随着这些物理区域增加，继电器基板的尺寸相应地变大，使得电子设备的尺寸变大。解决方案：在通过设置在中继基板上的多个连接器连接多个模块的情况下，在用于安装包括用于通过中继基板向各个逻辑模块供电的多个电源单元的电子设备的结构中，继电器基板和多个电源单元通过设置有用于与继电器基板连接的多个电源接头的电源连接基板和用于与多个电源单元连接的多个连接器来连接。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2010027412A Connection structure between printed wiring boards 审中-公开
标题翻译：打印接线板之间的连接结构
公开(公告)号：JP2010027412A
公开(公告)日：2010-02-04
申请号：JP2008188065
申请日：2008-07-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKAHIRA MITSURU , KAWADA ATSUMI , SEGUCHI KAZUHIRO
IPC分类号： H05K1/14
摘要： PROBLEM TO BE SOLVED: To provide printed wiring board connection structure capable of connecting electrically different printed wiring boards each other at low cost by a simple structure, in a small mounting space, without interposing a connector, i.e. the printed wiring board connection structure, capable of connecting electrically the different printed wiring boards each other by the simple structure, in the small mounting space. SOLUTION: A comb-shaped protrusion is provided in an outer shape of the daughter side printed wiring board, and a spring metallic contact is attached thereto. A slit-like through-hole connected to an inner layer is provided in the mother side printed wiring board for connecting electrically the daughter side printed wiring board, and the slit-like through-hole is engaged with the comb-shaped protrusion of the daughter side printed wiring board. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供能够以简单的结构以低成本连接电气不同的印刷电路板的印刷电路板连接结构，在小的安装空间中，而不插入连接器，即印刷线路板连接结构，能够在小的安装空间中通过简单的结构将不同的印刷电路板彼此电连接。解决方案：梳状突起设置在子侧印刷电路板的外形中，并且弹簧金属接触件附接到其上。在母侧印刷布线板上设置有与内层连接的狭缝状通孔，用于将子端印刷布线板电连接，并且狭缝状的通孔与女儿的梳形突起接合侧印刷线路板。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2007333547A Printed circuit board mounting structure and nuclear medicine diagnosis apparatus 有权
标题翻译：印刷电路板安装结构和核医学诊断设备
公开(公告)号：JP2007333547A
公开(公告)日：2007-12-27
申请号：JP2006165466
申请日：2006-06-15
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SHIMOIRISA TAKAHIRO , KAWADA ATSUMI , OZAWA FUSAAKI
IPC分类号： G01T1/161 , G01T1/24 , H05K1/14 , H05K3/36 , H05K9/00
CPC分类号： H05K1/14 , H05K7/1408 , H05K9/0062 , H05K2201/044 , H05K2201/2018
摘要： PROBLEM TO BE SOLVED: To provide a printed circuit board mounting structure, mounting a semiconductor element capable of detecting or transmitting light, electromagnetic wave, vibration and so on through a printed circuit board with high positional accuracy, and an electronic device such as a nuclear medicine diagnosis apparatus including the printed circuit board mounting structure.
SOLUTION: In this printed circuit board mounting structure, connectors provided on each of a plurality of slave printed circuit boards juxtaposed on a master printed circuit board fixed to a metal-made backboard are respectively inserted in a plurality of connectors juxtaposed on the master printed circuit board. Both ends near the semiconductor element mounted on the respective slave printed circuit boards are partially held between a first metal-made frame and a second metal-made frame and fixed there to achieve high positional accuracy.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种印刷电路板安装结构，通过具有高位置精度的印刷电路板安装能够检测或发射光，电磁波，振动等的半导体元件，以及电子设备作为包括印刷电路板安装结构的核医学诊断装置。解决方案：在该印刷电路板安装结构中，设置在并置在固定到金属制背板上的主印刷电路板上的多个从属印刷电路板中的每一个上的连接器分别插入并置在金属制背板上的多个连接器中主印刷电路板。安装在各自的从属印刷电路板上的半导体元件附近的两端部分地保持在第一金属制框架和第二金属制框架之间并固定在其上以实现高位置精度。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005277115A Chip capacitor mounting structure and printed wiring board 审中-公开
标题翻译：芯片电容安装结构和打印接线板
公开(公告)号：JP2005277115A
公开(公告)日：2005-10-06
申请号：JP2004088301
申请日：2004-03-25
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIZOE YUKIO , TAKAHIRA MITSURU , KAMISAKA AKIRA , MATSUMOTO TAKASHI , KAWADA ATSUMI , TSUNODA ATSUSHI , ONO TAKAYUKI
IPC分类号： H05K3/34 , H01L23/12 , H05K1/18
CPC分类号： H01L2224/16 , Y02P70/613
摘要： PROBLEM TO BE SOLVED: To reduce a power supply and ground noise caused by high performance and high frequency of a semiconductor device with a BGA package mounted on a printed wiring board, and to reduce a chip capacitor mounting area used for noise reduction. SOLUTION: As a mounting structure for connecting a chip capacitor 3 by solder on the power source of the backside of the mounting place of a printed wiring board connecting the BGA package 1 by solder and a through-hole pad for ground, the circuit connection distance of the power source and the ground is made shorter than that in a conventional structure. Consequently, resistance and inductance of wiring can be reduced and the power source and ground noise can be reduced. Furthermore, since mounting of the chip capacitor on an area near the BGA package in a conventional structure is eliminated, an area required for chip capacitor mounting can be greatly reduced. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了减少由安装在印刷电路板上的BGA封装的半导体器件的高性能和高频率引起的电源和接地噪声，并且减少用于降噪的片式电容器安装区域。解决方案：作为通过焊料在连接BGA封装1的印刷电路板的安装位置的背面的电源上的焊料连接片状电容器3的安装结构和用于接地的通孔焊盘，电源和地的电路连接距离比常规结构的短。因此，可以降低布线的电阻和电感，并且可以降低电源和接地噪声。此外，由于消除了在传统结构中将贴片电容器安装在BGA封装附近的区域，所以可以大大减少片式电容器安装所需的面积。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2011249731A Substrate connection structure and electronic device 有权
标题翻译：基板连接结构和电子设备
公开(公告)号：JP2011249731A
公开(公告)日：2011-12-08
申请号：JP2010124324
申请日：2010-05-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WAKAYAMA NOBUHIKO , KAWADA ATSUMI , TAKAHIRA MITSURU
IPC分类号： H05K1/14 , H05K7/14 , H05K7/20
摘要： PROBLEM TO BE SOLVED: To provide a substrate connection structure and an electric device capable of securing cooling performance to a device while saving space.SOLUTION: The substrate connection structure connects a plurality of circuit boards and includes: the plurality of circuit boards; a connection substrate arranged horizontally to a passage of cooling air discharged from an air blowing part to connect the circuit boards to each other; and a connector part which connects each of the plurality of circuit boards to the connection substrate. Each of the circuit boards and the connection substrate are arranged on the same plane.
摘要翻译：要解决的问题：提供一种能够在节省空间的同时确保设备的冷却性能的基板连接结构和电气设备。解决方案：基板连接结构连接多个电路板，包括：多个电路板; 水平地布置成从空气吹出部排出的冷却空气的通道的连接基板，以将电路板彼此连接; 以及将多个电路板中的每一个连接到连接基板的连接器部。每个电路板和连接基板被布置在同一平面上。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JPH07147092A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07147092A
公开(公告)日：1995-06-06
申请号：JP18110094
申请日：1994-08-02
申请人： HITACHI LTD
发明人： YAMASHITA HIROKI , ITOU HIROYUKI , KAWADA ATSUMI , SAITO TATSUYA , NAKANISHI KEIICHIRO , ISHIDA RIEKO , CHIBA TSUNEYO
IPC分类号： G11C11/414 , H03K19/0175
摘要： PURPOSE:To provide the semiconductor integrated circuit device having a transmission system capable of shortening the wiring delay in a signal transmission line having a long wiring length and high wiring resistance. CONSTITUTION:The wiring 1011 of the short wiring length among the wirings for signal transmission between the logic circuits of the semiconductor integrated circuit device is provided with a voltage driving circuit 101a and is commonly provided with the function of a signal reception circuit by the logic circuit 10b responding the voltage at the terminal of the wiring 1011. On the other hand, the terminal of the wiring 102 of the long wiring length, hence the large wiring resistance is subjected to voltage driving with the voltage driving circuit 101 according to the input voltage of the logic circuit 10a. This terminal is provided with a current sensing circuit 103 which senses the current flowing in from the wiring and converts the current to a voltage. The output resistance of the driving circuit and the input resistance of the current sensing circuit are made smaller than the DC resistance of the wiring.

10. 发明专利

JPH06177663A OPTIC/ELECTRIC CONVERSION TRANSISTOR CIRCUIT 失效
公开(公告)号：JPH06177663A
公开(公告)日：1994-06-24
申请号：JP32519792
申请日：1992-12-04
申请人： HITACHI LTD
发明人： TANAKA KATSUYA , YAMASHITA HIROKI , KAWADA ATSUMI
IPC分类号： H03F3/08
摘要： PURPOSE:To provide a grounded base optic/electric conversion transistor (TR) circuit which is less effected by a power supply voltage fluctuation. CONSTITUTION:A collector of a TR Q1 is connected to a power supply VCC 1 via a load resistor R1 and its emitter is connected to a power supply VEE1 at a connecting point N1 via a load resistor R2. Its base is connected to the power supply VCC1 via a load resistor R3 and connected to the N1 via diodes D1, D2. An anode of a photo diode PD is connected to a connecting point between the emitter and the load resistor R2 and a bias voltage VH is given to the cathode. The output signal is obtained from a connecting point OUT1 between the load resistor R1 and the collector. The grounded base optic/electric conversion TR circuit which is less effected by a power supply voltage fluctuation is realized by keeping the difference of voltages between the base of the TRQ1 and the point N1 constant by means of the diodes D1, D2.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式