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1. 发明专利

JPS54148457A Integral analog input device 失效
标题翻译：集成模拟输入设备
公开(公告)号：JPS54148457A
公开(公告)日：1979-11-20
申请号：JP5659178
申请日：1978-05-15
申请人： Hitachi Ltd
发明人： SHIMOYAMA KAZUHIKO , KITADA TAKAYOSHI , KATOU AKIYOSHI
IPC分类号： G06F3/05
摘要： PURPOSE: To eliminate the extenal noise when the analog signals are integrated and thus to reduce the error by varying the oscillation frequency which determines the sampling and integrating cycles.
CONSTITUTION: The internal control signals are produced by using external AC input 6 (such as commerical frequency) given from the subject system as the fundamental frequency. The zero point of input 6 is detected through zero-point detection circuit 10 to deliver basic clock 23. Receiving this output, divider circuit delivers division signal 13 which is necessary for the internal operation. Control circuit 18 performs the counting action for signal 13 and delivers a series of control signal 8 to control the integrating action, writing into register 4 and others. In this way, both the sampling and integrating cycles can be varied in accordance with the frequency variation of the subject system. Thus, the external noise can be eliminated, reducing the error caused by the noise.
COPYRIGHT: (C)1979,JPO&Japio
摘要翻译：目的：消除模拟信号的积分噪声，从而通过改变确定采样和积分周期的振荡频率来减小误差。构成：通过使用从主体系统给出的外部交流输入6（如商业频率）作为基频产生内部控制信号。通过零点检测电路10检测输入6的零点以传送基本时钟23.接收该输出时，分频电路传送内部操作所需的分频信号13。控制电路18对信号13进行计数动作，并输出一系列控制信号8，以控制积分动作，写入寄存器4等。以这种方式，采样和积分周期都可以根据被摄体系的频率变化而变化。因此，可以消除外部噪声，减少由噪声引起的误差。

2. 发明专利

JPS55103617A COMPUTER SYSTEM 失效
公开(公告)号：JPS55103617A
公开(公告)日：1980-08-08
申请号：JP1045679
申请日：1979-02-02
申请人： HITACHI LTD
发明人： KATOU AKIYOSHI
IPC分类号： G06F11/00 , G06F3/00 , G06F13/00
摘要： PURPOSE:To change-over a switch at a hot-line insertion and removal time of a print board not only to generate a response false signal in an interface circuit but also to make an alarm detection circuit ineffective. CONSTITUTION:In case of hot-line insertion and removal of the print board of circuit 2 for I/O device, selector switch 16 is turned on previously. Under the turning- on state, output S1 or OR circuit 13A for alarm circuit becomes a signal, which indicates always a normal operation, due to the signal from switch 16. Response signal generation circuit 14 is operated by I/O device selection signal S3. In case that switch 16 is turned off, NAND circuit 15 is not operated because of the failure of AND conditions. However, in case that switch 16 is turned on, NAND circuit 15 is operated due to the truth of AND conditions. Consequently, even for hot-line insertion and removal of the plug-in of the circuit for I/O device, central processing unit 3 is not stopped because a false response signal can be obtained from interface circuit 1.

3. 发明专利

JPS57183145A DATA TRANSMITTER 失效
公开(公告)号：JPS57183145A
公开(公告)日：1982-11-11
申请号：JP6697581
申请日：1981-05-06
申请人： HITACHI LTD
发明人： KATOU AKIYOSHI
IPC分类号： H04J3/24 , H04J3/16 , H04L5/22
摘要： PURPOSE:To transmit a large amount of data while varying the amount of transmitted information by providing a storage circuit, which corresponds to the amount of transmitted information, on a receiver side. CONSTITUTION:On the basis of the timing of a clock circuit 61, a counter circuit 62 operates. The contents of the counter circuit 62 are decoded by a decoding circuit 63. According to the decoding result, one of driving circuits 64 is selected. The selected driving circuit 64 transfers on-off information on an optional group of contacts 4 and an answer signal SA to a level converting circuit 11. After sending out a synchronizing signal S1, a parallel-serial converting circuit 12 sends out the count value of the counter circuit 62 as an address information signal S3. Then, the external answer signal SA and a data signal S2' consisting of pieces of on-off information on respective contacts are sent out in order. A receiving circuit 21 receives the signals from a transmission line 3 and sends out them to a serial-parallel converting circuit 22, an address discriminating circuit 71, and a timing control circuit 74. The data signal S2' to be stored is sent to a storage circuit 72, where it is stored.

4. 发明专利

JPS55153046A ANALOG INPUT DEVICE 失效
公开(公告)号：JPS55153046A
公开(公告)日：1980-11-28
申请号：JP5914979
申请日：1979-05-16
申请人： HITACHI LTD
发明人： KATOU AKIYOSHI , SHIRAISHI HISANORI
IPC分类号： H03M1/10 , G06F3/05
摘要： PURPOSE:To shorten the needed time of a data processing circuit, by enabling an analog input device to make sensor-by-sensor corrections. CONSTITUTION:Analog data are A/D-converted through level converting circuit 31 and input data selecting circuit 32 before being input to adding circuit 36. Zero- correction data set to every sensor by variable resistor 39 are stored in memory part 38 and a fixed value is input to adding circuit 36. Correction data for the inclination of the input data are similarly generated and then multiplied by zero-corrected input data in multiplying circuit 37. As a result, data having the zero-point and gain corrected for every input data can be input to a data processing circuit, so that software for data processing can be reduced.

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