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1. 发明专利

JP2009194676A Programmable logic device, construction method thereof, and using method thereof 有权
标题翻译：可编程逻辑器件，其构造方法及其使用方法
公开(公告)号：JP2009194676A
公开(公告)日：2009-08-27
申请号：JP2008034040
申请日：2008-02-15
申请人： Hiroshima Industrial Promotion Organization , 財団法人ひろしま産業振興機構
发明人： HIRONAKA TETSUO , HIRAKAWA NAOKI , YOSHIHARA TOSHINORI
IPC分类号： H03K19/177
摘要： PROBLEM TO BE SOLVED: To avoid propagation delay of data by enabling discrete wiring between basic logic blocks, and to achieve reduction of the area of PLD by allowing SRAM of the basic logic block to be a single port SRAM.
SOLUTION: The basic logic block constituting PLD is provided with: additional wiring of address data pair where input/output data line for logic circuit is distributed to each bit; an address line; and a data line. The additional wiring can be added only to a wanted basic logic block as required. The address data pair, address line, and data line may be combined to constitute a single PLD.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了通过在基本逻辑块之间实现分立布线来避免数据的传播延迟，并且通过使基本逻辑块的SRAM成为单端口SRAM来实现PLD的面积的减小。解决方案：构成PLD的基本逻辑块提供：地址数据对的附加布线，其中用于逻辑电路的输入/输出数据线分配给每个位; 地址线和数据线。额外的接线只能根据需要添加到想要的基本逻辑块。地址数据对，地址线和数据线可以组合以构成单个PLD。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2007213641A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2007213641A
公开(公告)日：2007-08-23
申请号：JP2006029910
申请日：2006-02-07
申请人： Hiroshima Industrial Promotion Organization , 財団法人ひろしま産業振興機構
发明人： HIRONAKA TETSUO , TANIGAWA KAZUYA , YAMABE HIROKI , ASAO MUNETAKA , SUZUKI KEISUKE
IPC分类号： G11C11/41 , G11C11/417
摘要： PROBLEM TO BE SOLVED: To provide a memory capable of input/output of arbitrary parallel data of word width N and input/output of arbitrary serial data of digit width Nd. SOLUTION: A memory cell comprising a parallel wordline, a serial wordline, a parallel bit line and serial bit line is arranged in a shape of a matrix and an address of the memory cell is assigned so as to be able to access a plurality of lines of memory cells by selecting one serial wordline. Thereby, a plurality of digit serial data can be inputted or outputted simultaneously to one memory. Also a plurality of data of arbitrary digit widths can be simultaneously processed by setting up a plurality of memories and arranging wiring of digit serial data in order. Consequently the memory capable of conversion of the digit width and input/output of parallel data and serial data can be provided. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够输入/输出字宽N的任意并行数据和数字宽度Nd的任意串行数据的输入/输出的存储器。解决方案：包括并行字线，串行字线，并行位线和串行位线的存储器单元被布置成矩阵的形状，并且分配存储器单元的地址以便能够访问通过选择一个串行字线来存储多行存储器单元。因此，可以将多个数字串行数据同时输入或输出到一个存储器。而且，可以通过设置多个存储器并且依次排列数字串行数据的布线来同时处理多个任意数字宽度的数据。因此，可以提供能够转换数字宽度和并行数据和串行数据的输入/输出的存储器。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006260127A Interconnection network and multiport memory using the same 审中-公开
标题翻译：互连网络和使用相同的多媒体存储器
公开(公告)号：JP2006260127A
公开(公告)日：2006-09-28
申请号：JP2005076253
申请日：2005-03-17
申请人： Hiroshima Industrial Promotion Organization , Hiroshima Univ , 国立大学法人広島大学 , 財団法人ひろしま産業振興機構
发明人： MATTHEW HANS JUERGEN , KOIDE TETSUSHI , HIRONAKA TETSUO , INOUE TOMOHIRO
IPC分类号： G06F12/06
摘要： PROBLEM TO BE SOLVED: To provide an interconnection network that quickly and simply addresses a many-to-many assignment problem, and a multiport memory using the same. SOLUTION: The multiport memory 10 comprises the interconnection network 11 having input ports 12 and output ports 13, and memory blocks 14 each connected to the interconnection network 11 via an output part 18 comprising a plurality of output ports 13. The interconnection network 11 may be EBSF 30. Outputs of the EBSF 30 are not bound to a single port but output independently to the memory blocks 14. The EBSF 30 can thus be used as an interconnection network and an arbitration function. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供快速简单地解决多对多分配问题的互连网络，以及使用该互连网络的多端口存储器。解决方案：多端口存储器10包括具有输入端口12和输出端口13以及各自经由包括多个输出端口13的输出部分18连接到互连网络11的存储器块14的互连网络11.互连网络 11可以是EBSF 30.EBSF 30的输出不限于单个端口，而是独立于存储器块14输出。因此，EBSF 30可以用作互连网络和仲裁功能。版权所有（C）2006，JPO＆NCIPI

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