专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2009259392A Memory architecture 审中-公开
标题翻译：内存架构
公开(公告)号：JP2009259392A
公开(公告)日：2009-11-05
申请号：JP2009151839
申请日：2009-06-26
申请人： Hans-Juergen Mattausch , Siemens Ag , シーメンスアクチエンゲゼルシヤフトSiemens Aktiengesellschaft , マタウシュハンス−ユルゲン
发明人： MATTAUSCH HANS-JUERGEN
IPC分类号： G11C11/41 , G11C11/401
CPC分类号： G11C11/41
摘要： PROBLEM TO BE SOLVED: To provide a memory architecture with multilevel hierarchy structure having a plurality of external ports.
SOLUTION: Multi-port memory architecture having a multilevel hierarchy typically has one-port memory cells in the lowermost hierarchical level. The memory blocks in the respectively higher hierarchical levels are each made up of memory blocks from the next lower hierarchical level. By the defined multi-port memory architecture with multilevel hierarchy, the required surface area on the chip is reduced. The memory blocks in the hierarchical levels can, depending on requirement, be disposed in a memory block matrix in a switching network, a banking technique arrangement, and so forth. Thus, depending on the desired application, the greatest possible freedom of design is provided. The multi-port memory architecture also has a circuit for handling access conflict.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有多个外部端口的多层次结构的存储器架构。解决方案：具有多层次层次结构的多端口存储器架构通常具有最低层次级别的单端口存储器单元。分别在较高分层级别的存储块分别由下一较低等级的存储块组成。通过具有多层次层次结构的定义的多端口存储器架构，芯片上所需的表面积减小。根据需要，分级级别中的存储器块可以被布置在交换网络中的存储器块矩阵中，银行技术装置等中。因此，根据期望的应用，提供最大可能的设计自由度。多端口存储器架构还具有用于处理访问冲突的电路。版权所有（C）2010，JPO＆INPIT

IPRDB

热门服务

关于我们

友情链接

联系方式