会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明专利
    • JPH05300795A
    • 1993-11-12
    • JP12129792
    • 1992-04-15
    • MITSUBA ELECTRIC MFG CO
    • YAMAGISHI TOMOOSHIGEMATSU KATSUYA
    • B60N2/06H02P5/00H02P7/67
    • PURPOSE:To simultaneously operate two motor driving circuits by providing an interlock circuit for inhibiting an operation of the driving circuit in which a CPU not selected by a selection switch is not concerned. CONSTITUTION:Motor drive controllers 1, 51 for motor-driven power seats having motors 6, 56 for displacing a driver's seat and an assistant driver's seat of a vehicle in sliding directions have selection switches 5 for selecting manual or automatic operation for one of the driver's seat and the assistant driver's seat. In this case, a sub-driving circuit 20 of another system from a main driving circuit 2 connected to a CPU 2 is provided in the controller 1 (similar in the 52). The operation of the sub-driving circuit 20 is restricted by an interlock circuit which includes a transistor 19 to be turned ON only when the other input terminal of a NOR gate 22 is grounded by the switch 5 and a state of an output terminal of FF24 becomes a low level.
    • 7. 发明专利
    • SECURITY CONTROLLER
    • JPH0717359A
    • 1995-01-20
    • JP18938593
    • 1993-06-30
    • MITSUBA ELECTRIC MFG CO
    • OGINO SEIICHISHIGEMATSU KATSUYAOGAWA TOMOYUKI
    • B60R25/00B60R25/104B60R25/30
    • PURPOSE:To prevent the generation of alarm due to the erroneous operation by installing an indicator which represents the operation state of a CPU and allowing the supply of an alarm output only in the case where the signal representing the operation of the CPU is supplied from an indicator signal detecting circuit. CONSTITUTION:When a CPU operates in a monitored state, an indicator signal is outputted from the B terminal of the CPU, and the signal is inputted into an indicator 11 through an indicator output circuit 10, and a diode LED 1 is flashed. At the same time, the above signal is inputted into an indicator signal detecting circuit 13, and an H-level signal is outputted to the second input terminal of a two-input AND gate G1 by the operations of the transistors Tr1-Tr4. While, in a nonmonitored state, an L-level signal is outputted from the B terminal of the CPU 1, and an L-level signal is outputted at the second input terminal of the two-input AND gate G1. In this case, the gate G1 operates an alarm means 14 through an output circuit 4 only in the case where both the first and second inputs are at the H-level, i.e., only in the monitored state. G1. In this case, the gate G1 operates an alarm means.