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1. 发明专利

JP2003224203A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS FABRICATING METHOD 审中-公开
公开(公告)号：JP2003224203A
公开(公告)日：2003-08-08
申请号：JP2002019159
申请日：2002-01-28
申请人： HITACHI LTD , NEC CORP , NEC ELECTRONICS CORP
发明人： NAKAMURA YOSHITAKA , ASANO ISAMU , IIJIMA SHINPEI , HIRATANI MASAHIKO , SAKUMA HIROSHI
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To enhance the characteristics of a semiconductor integrated circuit device by reducing the leak current of a capacitor element employed in a DRAM memory cell, or the like. SOLUTION: A capacitor element C for storing information connected with an MISFET Qs for transferring information in a memory cell forming region through plugs 20 and 39 is fabricated by forming a lower electrode 43a of an Ru film in the hole 42 of a silicon oxide film 41, depositing a tantalum oxide film on the lower electrode 43a and subjecting it to first heat treatment in an oxidizing atmosphere at a temperature high enough to repair oxygen defects but having no effect on the material underlying the tantalum oxide film, and to second heat treatment in an inert atmosphere at a temperature (not higher than 650°C) not crystallizing the tantalum oxide completely but higher than the temperature of subsequent process, and then forming an upper electrode 4c of a multilayer film of an Ru film and a W film on a capacitor insulation film 44b of the tantalum oxide. COPYRIGHT: (C)2003,JPO

2. 发明专利

JP2003078029A Semiconductor integrated circuit device and manufacturing method therefor 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：JP2003078029A
公开(公告)日：2003-03-14
申请号：JP2001263734
申请日：2001-08-31
申请人： Hitachi Ltd , Nec Corp , 日本電気株式会社 , 株式会社日立製作所
发明人： IIJIMA SHINPEI , SAKUMA HIROSHI
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/285 , H01L27/108
CPC分类号： H01L28/60 , H01L21/28518 , H01L27/10814 , H01L28/55 , H01L28/91
摘要： PROBLEM TO BE SOLVED: To prevent defects that oxygen through a lower electrode oxidizes the surface of a silicon plug at a lower layer, and that the oxide layer of high resistance is formed when a dielectric film formed on the lower electrode of a capacitive element in DRAM is thermally treated in an oxygen atmosphere.
SOLUTION: Since a polycrystalline silicon film 28 is formed along the inner wall of a groove 27 where the capacitive element is formed and the polycrystalline silicon film 28 is brought into contact with the lower electrode 29 in the whole inner wall of the groove 27, oxygen intruding into the lower electrode 29 at the time of heat treating a tantalum oxide film 32 is consumed in the interface of the polycrystalline silicon film 28 and the lower electrode 29, and it is prevented from reaching the surface of a plug 22.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了防止通过下部电极的氧氧化下层的硅插塞的表面的缺陷，并且当形成在电容元件的下部电极上的电介质膜时，形成高电阻的氧化物层在氧气氛中对DRAM进行热处理。解决方案：由于沿形成电容元件的凹槽27的内壁形成多晶硅膜28，并且多孔硅膜28在凹槽27的整个内壁中与下电极29接触，因此氧气在多晶硅膜28和下电极29的界面中消耗氧化钽膜32的热处理时侵入下电极29，并且防止其到达插塞22的表面。

3. 发明专利

JP2002270794A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED- CIRCUIT DEVICE 失效
公开(公告)号：JP2002270794A
公开(公告)日：2002-09-20
申请号：JP2001062909
申请日：2001-03-07
申请人： HITACHI LTD , NEC CORP
发明人： IIJIMA SHINPEI , SAKUMA HIROSHI , HIRATANI MASAHIKO
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent the nonconformity that oxygen which has permeated a lower electrode oxidizes a barrier layer and forms a high-resistance layer when a dielectric film on the lower electrode of the capacitance element of a DRAM, is heat-treated in an oxygen atmosphere. SOLUTION: The lower electrode 31 which is composed of a TaN film, and an Ru film deposited on its upper part is constituted at the inside of a groove 27 formed on a silicon oxide film 24. In succession, a tantalum oxide film 32a is deposited on the upper part of the lower electrode 31 by CVD method. After that, in order to crystallize the film 32a and to improve its film quality, it is heat-treated at 300 to 400 deg.C in an oxygen-containing atmosphere. Thereby, the nonconformity of a high-resistance oxide layer being formed between a plug 22 composed of polycrystalline silicon and the lower electrode 31 is prevented.

4. 发明专利

JPS628196A DRIVING OF DISPLAY UNIT AND OUTPUT INVERTER FOR DRIVING 失效
公开(公告)号：JPS628196A
公开(公告)日：1987-01-16
申请号：JP14861585
申请日：1985-07-05
申请人： NEC CORP
发明人： SAKUMA HIROSHI
IPC分类号： G09G3/28 , G09G3/288 , G09G3/291 , G09G3/292 , G09G3/296

5. 发明专利

JPH064614A LOGICAL SIMULATION DEVICE 失效
公开(公告)号：JPH064614A
公开(公告)日：1994-01-14
申请号：JP15971192
申请日：1992-06-18
申请人： NEC CORP
发明人： SAKUMA HIROSHI
IPC分类号： G06F17/50 , G06F15/60
摘要： PURPOSE:To enable verification in the case where plural input signals have change allowable periods by single logical simulation by providing an input change allowable period propagating means to be stored in an input signal change allowable period storage means. CONSTITUTION:This logical simulation device is provided with an input change allowable period storage means 105 storing the change allowable period of the internal signal of a logic circuit and an input change allowable period propagating means 103 storing the change allowable period corresponding to a first signal which is stored in the input change allowable period storage means 105 and is to be the cause of the change of a second signal as the change allowable period corresponding to this second signal in the input signal change allowable period storage means 105 when an arithmetic circuit 102 decides that a change occurs in the second signal. The change allowable period of an input signal is propagated with the change of the signal inside the circuit caused by this input signal. Therefore, the verification in the case where plural input signal have change allowable periods can be performed by one time logical simulation.

6. 发明专利

JPH04167179A LOGIC SIMULATING METHOD 失效
公开(公告)号：JPH04167179A
公开(公告)日：1992-06-15
申请号：JP29607190
申请日：1990-10-31
申请人： NEC CORP
发明人： SAKUMA HIROSHI
IPC分类号： G06F11/25 , G06F11/26 , G06F17/50
摘要： PURPOSE:To realize accurate verification for an arbitrary sequential circuit by providing a timing verification function to verify whether or not the signal change of a pair of signals on a logic circuit satisfy a constraint condition decided in advance. CONSTITUTION:Since a data signal that is a reference signal is changed at a time t 1, a start event is scheduled at the time t 1 by a start event schedule means 3. Since the time is equivalent to the present time t 1, a flag representing the execution of verification is set at a verification state storage means 8 by a vetification start means at the following step, and also, a completion event is scheduled at a time before the present time t 1 by d 1. Furthermore, when a time progresses and arrives at a time (t 1+d 1), a scheduled completion event is started up, and a flag representing no verification is set at the verification state storage means 8. Thereby, it is possible to verify even the constraint condition at a timing for the sequential circuit provided with arbitrary device structure.

7. 发明专利

JPH04114279A LOGIC SIMULATION METHOD 失效
公开(公告)号：JPH04114279A
公开(公告)日：1992-04-15
申请号：JP23479490
申请日：1990-09-05
申请人： NEC CORP
发明人： SAKUMA HIROSHI
IPC分类号： G06F11/25 , G06F11/26 , G06F17/50
摘要： PURPOSE:To exactly verify bus competition without error by providing an allowable time width storing means to store bus competition allowable time width set in advance and a competing state storing means to store a flag showing whether a bus is in a competing state at certain time during simulation or not. CONSTITUTION:An allowable time width storing means 16 stores the allowable time width of bus competition designated to a bus to be the object of verification and is set in advance before starting the simulation. A competing state storing means 17 stores the flag showing whether the bus is in the competing state at certain time during the simulation or not, and sets a flag showing that all the buses are not in a verification state, before starting the simulation. An event possessing means 11 possesses one event at the current simulation time and decides whether the event is finished or not and when it is finished, an end processing is executed. Thus, the competition of the bus can be verified while considering the allowable condition.

8. 发明专利

JPS62267797A DRIVING OF PLASMA DISPLAY UNIT 失效
公开(公告)号：JPS62267797A
公开(公告)日：1987-11-20
申请号：JP11217386
申请日：1986-05-15
申请人： NEC CORP
发明人： SAKUMA HIROSHI
IPC分类号： G09G3/28 , G09G3/288 , G09G3/291 , G09G3/293 , G09G3/294

9. 发明专利

JPS61241677A DIAGNOSTIC SYSTEM GENERATING CIRCUIT FOR INSPECTING LOGICAL CIRCUIT 失效
公开(公告)号：JPS61241677A
公开(公告)日：1986-10-27
申请号：JP8391885
申请日：1985-04-19
申请人： NEC CORP
发明人： SAKUMA HIROSHI
IPC分类号： G06F11/22 , G01R31/28
摘要： PURPOSE:To enable self diagnosing of an integrated circuit by selecting output signals of each register according to the number of input signals of the part of the circuit that becomes an object of inspection. CONSTITUTION:In the case where diagnostic system of the part of a circuit having the number of input signals (m), it is enough to select (m) output signals of a shift register 1. For instance, supposing that output signals of registers 11-1m are to be selected, switching signals of logic '1' are supplied to switching circuits 101-10m of a switching logical circuit 10, and switching signals of logic '0' are supplied to switching circuits 10m+1-10n through a signal line 7. At the same time, set and reset signals are supplied from a signal line 5 to registers 11-1m, and only the register 11 of the first stage is set to logical value '1' and all other registers 12-1m are set to logical value '0'. Then, clock pulses are inputted successively from a clock signal line 8, and a pseudo random pattern is supplied from the signal line 6 of registers 11-1m of the first step to m-th step to the part of a circuit to be diagnosed, and self-diagnosis of an integrated circuit is performed.

10. 发明专利

JPS59176840A Adder 失效
标题翻译： ADDER
公开(公告)号：JPS59176840A
公开(公告)日：1984-10-06
申请号：JP5123083
申请日：1983-03-26
申请人： Nec Corp
发明人： SAKUMA HIROSHI
IPC分类号： G06F7/38 , G06F7/00 , G06F7/507 , G06F11/267
CPC分类号： G06F11/2226 , G06F7/50
摘要： PURPOSE:To diagnose an adder by supplying 1 to one side of the input terminals of the adder, and the output of the adder to the other input terminal in a diagnosis mode respectively to perform addition calculation for each clock input, and at the same time, giving +1 to a counter to compare the output of addition with the count value. CONSTITUTION:In a diagnosis mode a counter 110 and a register 109 are cleared with the signal given from an input signal line 106. Then the signal which starts the diagnosis is given from an input signal line 105, and a clock P3 is produced from a clock penerator 107. A multi-switch 114 is controlled with the output signal of a ternary logical circuit 111. This switch 114 supplies 1 to a line 113 and the lowest bit line of the output of an adder 103 to the line 112 respectively via a register 109 respectively. Therefore the output of the adder 103 receives +1 for each input of the clock and has the same value as the counter 110 as long as a normal state is obtained. When a carry is delivered from the counter 110, the circuit 111 switches the connection between lines 113 and 112 to perform the same operation.
摘要翻译：目的：通过在诊断模式下分别向加法器的输入端子1〜1端提供加法器输出到另一输入端子来诊断加法器，以对每个时钟输入进行加法运算，同时，给予一个计数器+1，以将加法的输出与计数值进行比较。构成：在诊断模式中，用输入信号线106给出的信号清除计数器110和寄存器109.然后，从输入信号线105给出开始诊断的信号，并从时钟P3产生时钟P3 时钟发生器107.多开关114由三元逻辑电路111的输出信号控制。该开关114分别通过一个第一逻辑电路111将一个线113和加法器103的输出的最低位线分别提供给线112，寄存器109。因此，加法器103的输出对于时钟的每个输入接收+1，并且只要获得正常状态，就具有与计数器110相同的值。当从计数器110传送进位时，电路111切换线113和112之间的连接，以执行相同的操作。

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