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1. 发明专利

JPH04245618A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04245618A
公开(公告)日：1992-09-02
申请号：JP1058491
申请日：1991-01-31
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NITTA KYOYA , MORI SHIGEKI
IPC分类号： H01L21/027
摘要： PURPOSE:To improve precision and yield of lithography using a charged particle beam and multilayer resist. CONSTITUTION:In the manufacturing method of a semiconductor integrated circuit device wherein multilayer resist composed of a flattened film 7, an organic film 8, an intermediate film 9, and resist 10 is used, the flattened film 7 is composed of conducting organic material like polyvinyl carbazole resin, photosensitive agent like naphthoquinone diazide, and crosslinking agent like epoxy resin. The organic film 8 is composed of cresol resin, photosensitive agent like indene bisazide, and nonionic surface active agent like aromatic fluorocarbon. The intermediate film 9 is composed of inorganic material like spin-on-glass. The resist 10 is composed of electron beam resist of a positive type or a negative type.

2. 发明专利

JPH0451244A ELECTRON BEAM RESIST 失效
公开(公告)号：JPH0451244A
公开(公告)日：1992-02-19
申请号：JP15979190
申请日：1990-06-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MORI SHIGEKI , NITTA KYOYA , MORITA MASAYUKI , TONOKAWA HIROSHI
IPC分类号： G03F7/075 , H01L21/027
摘要： PURPOSE:To eliminate the need for an intermediate layer with a lower layer resist for flattening steps and to decrease the number of processes of resist processing by using a silanol compd. and an acid precursor as essential components. CONSTITUTION:The lower layer resist 3 for flattening steps consisting of a novolak resin and the electron beam resist 4 are successively applied on a silicon oxide film 2 of the main surface of a semiconductor wafer 1 consisting of a silicon single crystal. The electron beam resist is formed by dissolving the silanol compd. and the acid precursor in an org. solvent. The acid precursor is compounded at a ratio of 1 to 50wt.% with 50 to 99wt.% silanol compd. The acid liberated from the acid precursor of the exposed part changes to a catalyst and generate the condensation reaction of the silanol compd. if this electron beam resist is irradiated with radiations. Alkaline-insoluble polysiloxane is then formed. Only the unexposed part is then dissolved and the prescribed resist patterns are obtd. if the alkaline developing soln. is acted thereon.

3. 发明专利

JPH088151A MANUFACTURE FOR SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE USING THE WAFER 失效
公开(公告)号：JPH088151A
公开(公告)日：1996-01-12
申请号：JP13919494
申请日：1994-06-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NITTA KYOYA
IPC分类号： H01L21/027 , G03F7/20 , H01L21/02
摘要： PURPOSE:To provide a method for manufacturing a semiconductor wafer with a highly accurate pattern and a finely patterned semiconductor device with accuracy in pattern dimensions. CONSTITUTION:In a semiconductor wafer 1, each pattern for IC chip formation regions 1c is shifted 90 degrees from each other. Then, dimensional errors caused by thermal expansion of these formation regions 1c are generated in different directions and canceled to each other, and the semiconductor wafer 1 has an accurately patterned structure. Since each pattern of the IC chip forming region 1c is shifted 90 degrees by suing an aligner a fine patterning step is carried out with accuracy in dimensions in a semiconductor manufacturing step.

4. 发明专利

JPH0536583A ALIGNMENT METHOD AND MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0536583A
公开(公告)日：1993-02-12
申请号：JP19008391
申请日：1991-07-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MORIUCHI NOBORU , SHIRAI SEIICHIRO , NITTA KYOYA , HIDA HIROYUKI
IPC分类号： G03F9/00 , H01L21/027 , H01L21/30
摘要： PURPOSE:To perform an alignment operation among many layers without increasing an alignment margin in the alignment operation of pattern positions in an exposure process as the manufacturing process of a semiconductor integrated circuit device. CONSTITUTION:In a process 101, individual alignment marks for a diffusion-layer pattern and a gate-electrode pattern are first detected, and positional coordinates of the individual alignment marks are computed. In a process 102, sets of the positional coordinates, of the alignment marks, which have been computed in the process 101 are averaged, and reference positional coordinates for alignment use of contact hole patterns are computed. After that, in a process 103, a reticle and a semiconductor wafer are aligned relatively on the basis of the reference positional coordinates, for alignment use of the contact hole patterns, which have been computed in the process 102.

5. 发明专利

JPH04280415A ELECTRON BEAN DRAWING DEVICE 失效
公开(公告)号：JPH04280415A
公开(公告)日：1992-10-06
申请号：JP4321891
申请日：1991-03-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NITTA KYOYA , KATO MAKOTO
IPC分类号： H01L21/027
摘要： PURPOSE:To obtain an electron beam drawing device which prevents a contact or a discontinuity of a circuit pattern from occurring and enables yield to be improved. CONSTITUTION:A vacuum cleaner 7 for sucking a foreign object such as a resist 1 which is generated when setting up an earth pin 3 on a wafer substrate 2 is provided, this vacuum cleaner 7 is in a hollow structure where a suction path 5 is formed along an axial direction with the earth pin 3 within the inside, and then a suction port 6 is formed on an outer-periphery surface of the earth pin 3.

6. 发明专利

JPH03253019A RESIST PROCESSING 失效
公开(公告)号：JPH03253019A
公开(公告)日：1991-11-12
申请号：JP4938290
申请日：1990-03-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NITTA KYOYA , SHIRAI SEIICHIRO , HAYAKAWA HAJIME
IPC分类号： G03F7/11 , G03F7/26 , H01L21/027 , H01L21/768
摘要： PURPOSE:To avoid the cracking in pattern corner parts even if polyvinylcarbazole is used and the first and second layers are dryetched by a method wherein heating or ultraviolet irradiation process or both of them are performed after the formation of the first layer. CONSTITUTION:In order to form a resist, firstly, the first layer (bottom layer) 4 containing polyvinylcarbazole is formed on a substrate 3 by spincoating process. Next, the layer 4 is baked for specific time and dried up simultaneously after irradiating it with ultraviolet ray (UV) for specific time, the second layer (intermediate layer) 5 is formed on the surface of the layer 4 also by spin- coating process. Next, after baking the layer 5, the third layer (topmost layer) 6 is formed on the layer 5 and then the layer 6 is baked. Finally, a pattern is formed to be tranferred (dryetched) to the underneath layer (bottom layer) 4. Through these procedures, the practice of surface oxidation, acceleration of resist bridging, enhancement of bond properties, relief of inner stress, etc., are made feasible. Resultantly, the cracking in the pattern corner parts of the layer 5 during the dryetching process of the layers 5, 6 can be avoided, thereby enabling the yield to be augmented.

7. 发明专利

JPH0357210A METHOD AND APPARATUS FOR PATTERN LITHOGRAPHY 失效
公开(公告)号：JPH0357210A
公开(公告)日：1991-03-12
申请号：JP19149489
申请日：1989-07-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MORI SHIGEKI , AONO TAKESHI , NITTA KYOYA , MORITA MASAYUKI , HAYAKAWA HAJIME
IPC分类号： H01L21/027
摘要： PURPOSE:To enhance a pattern size accuracy and a pattern position accuracy by a method wherein a deflection amount of an energy beam and a focal-point position with reference to an object to be drawn are corrected according to a size of the energy beam. CONSTITUTION:In an electron-beam direct drawing apparatus 1, a semiconductor wafer 3 in which a resist for electron-beam drawing use has been applied to, e.g. its surface is placed detachably on an X-Y stage 2. An electron beam source 4 is installed at the upper part of the X-Y stage 2; an electron beam E is radiated toward the semiconductor wafer 3. A variable shaping lens part 5 is constituted so as to continuously change a beam size and a shape; a focusing deflection lens part 6 is constituted so as to deflect the electron beam E to a prescribed drawing position and so as to set a focal-position. A deflection control circuit 14 corrects a deflection amount on the basis of a numerical data according to the beam size; a focal-point control circuit 15 corrects the focal-point position on the basis of the numerical data according to the beam size.

8. 发明专利

JPH01105534A ELECTRONIC BEAM EXPOSURE SYSTEM 失效
公开(公告)号：JPH01105534A
公开(公告)日：1989-04-24
申请号：JP26154887
申请日：1987-10-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： AONO TAKESHI , MORI SHIGEKI , NITTA KYOYA
IPC分类号： G03F7/20 , H01L21/027 , H01L21/30
摘要： PURPOSE:To improve the dimensional accuracy of a figure by controlling the shape and rotation angle of the photoelectric surface of electronic beams or the strength of an astigmatic correction lens according to the change of area of the photoelectric surface of electronic beams to correct the astigmatism of electronic beams. CONSTITUTION:An astigmatism correction part 20 reads correction data from a correction data storing part 21 according to the information on the area of the photoelectric surface of an electronic beam 6 in the control information of the electro-optical system sent out from a pattern generation part 17. The correction part 20 accordingly increases or decreases the length of each side of the photoelectric surface of an electronic beam 6 via a shaping deflector control part 18. This correction and the correction of the rotation angle of the electronic beam 6 via a beam rotation lens control part 19 are combined with each other. The control such that the astigmatism in the electronic beam 6 irradiated to an exposed object 2 becomes the minimum is performed. This enables the dimensional accuracy of the figure to be improved.

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