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1. 发明专利

JPH06216272A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06216272A
公开(公告)日：1994-08-05
申请号：JP23215493
申请日：1993-09-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HARADA TAKU , YOSHIHARA KAZUHIRO , MASUZAWA KAZUTAKA , HAYASHI TERUYOSHI , KUMAZAWA ATSUSHI , NAGAI KENJI , NISHIUMA MASAHIKO , KAMATA CHIYOSHI
IPC分类号： H01L23/12 , H01L23/13 , H01L23/498 , H01L23/66
摘要： PURPOSE:To realize matching of characteristic impedance of signal transmitting lines in a package for mounting a semiconductor chip on which ultra-high speed LSI is formed. CONSTITUTION:One end of a signal transmitting line 203 formed on the main surface of a package substrate 204 is extended up to the area just under a pad formed on the main surface of a semiconductor chip 201 and is then electrically connected to a pad on a semiconductor chip 201 via a bump electrode. Moreover, the other end of the signal transmitting line 203 is extended up to the external circumference of the main surface of the package substrate 204 and is then coupled with an external lead 205.

2. 发明专利

JPH09252077A SEMICONDUCTOR DEVICE, MOUNTING METHOD THEREOF, AND ELECTRONIC DEVICE PROVIDED THEREWITH 失效
公开(公告)号：JPH09252077A
公开(公告)日：1997-09-22
申请号：JP6046696
申请日：1996-03-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： EMATA KOJI , OKINAGA TAKAYUKI , WADA TAMAKI , SHIMOISHI TOMOAKI , NISHIUMA MASAHIKO , MASUDA MASACHIKA
IPC分类号： H01L25/18 , H01L23/50 , H01L25/10 , H01L25/11 , H05K3/30 , H05K3/34 , H01L23/52 , H01L25/00
摘要： PROBLEM TO BE SOLVED: To provide a technique which is capable of reducing a mounting structure in thickness by setting a package large enough in angle of inclination when the packages are mounted as they are tilted so as to be enhanced in mounting density. SOLUTION: A semiconductor device 1 is composed of a mounting board and a package 2 which is tilted in posture and mounted on the board through the intermediary of leads 3, where a pair of support leads 4 are led out from the sides 2B and 2C other than the side 2A of the package 2 where the leads 3 are led out so as to keep the package 2 tilted. By this setup, the package 2 can be optionally set at an angle θ of inclination by the support leads 4.

3. 发明专利

JPH02113562A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02113562A
公开(公告)日：1990-04-25
申请号：JP26604788
申请日：1988-10-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , TSUBOI TOSHIHIRO , HONDA ATSUSHI
IPC分类号： H01L23/473
摘要： PURPOSE:To enable direct cooling via a base, and improve heat dissipating efficiency by forming a cavity part on the rear of a semiconductor pellet in a package, and forming a refrigerant-input-output hole linking with the cavity part. CONSTITUTION:A cavity part 13 is formed on the rear of a semiconductor pellet 10 in a package 12, and a refrigerant-input-output hole 15a linking with the cavity part 13 is formed. As a result, by refrigerant fed through the refrigerant-input-output hole 15a, the semiconductor pellet 10 can be directly cooled. In the case where a substrate 11 retaining the semiconductor pellet 10 exists, the pellet 10 can be cooled via the substrate 11. Since the cooling is executed inside the cooling package 12, the heat generating in the semiconductor pellet 10 is dissipated without passing many material members and interfaces. Thereby, heat dissipating efficiency is increased.

4. 发明专利

JPH0236541A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0236541A
公开(公告)日：1990-02-06
申请号：JP18564688
申请日：1988-07-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TSUBOI TOSHIHIRO , NISHIUMA MASAHIKO , HONDA ATSUSHI
IPC分类号： H01L21/52
摘要： PURPOSE:To eliminate uplifting a pellet or shifting its position and to improve the positional accuracy of the pellet by a method wherein recessed parts and protruding parts are formed on a die pad on a package base and the recessed parts are used as grooves for venting use to the outside at a time when a solvent being contained in a paste is turned into gas at the time of heating and curing and is volatilized. CONSTITUTION:A plurality of quadrilateral protruding parts 11 are arranged on a die pad on a package base 5 in a lattice type at proper intervals interposing recessed parts 10 between them. At the time of pellet attachment, a paste 8 is applied on the die pad with the protruding and recessed parts 10 and 11 formed thereon by a potting technique. A pellet 7 is placed on the die pad and the paste 8 is heated and cured by a heating furnace. The parts 10 are used as grooves for venting use and a volatile solvent (gas) in the paste 8 can be released outside of the die pad at the time of pellet attachment.

5. 发明专利

JPH01137660A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01137660A
公开(公告)日：1989-05-30
申请号：JP29524187
申请日：1987-11-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TSUBOI TOSHIHIRO , NISHIUMA MASAHIKO , HONDA ATSUSHI
IPC分类号： H01L23/50 , H05K3/34
摘要： PURPOSE:To connect a plurality of rows of leads in parallel to surface mount the leads of a plurality of lead frames on a mounting substrate, and to mount the leads in high density by providing a lead frame structure in which the leads of the plurality of lead frames are superposed through insulating adhesives. CONSTITUTION:A lead frame structure 4 in which a second lead frame 2 is superposed by adhering with an insulating adhesive 3, such as polyimide resin on a first lead frame 1 is employed as a normal lead frame. Then, the lead frames 1, 2 are connected in two rows, and can be surface mounted on a mounting substrate 8. Thus, the number of pins of one package is increased, thereby mounting them in high density.

6. 发明专利

JPH08125112A SEMICONDUCTOR DEVICE AND PRODUCTION THEREOF 失效
公开(公告)号：JPH08125112A
公开(公告)日：1996-05-17
申请号：JP26213094
申请日：1994-10-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
摘要： PURPOSE: To realize multilayer mounting of a plurality of semiconductor elements by mounting a second semiconductor element having same dimensions as a first semiconductor device provided with a lead supporting structure and electrodes protruding higher than the lead, on the first semiconductor element and then connecting the protruding electrodes with the electrodes of the first semiconductor element. CONSTITUTION: One stage of balls 3a are formed, while being compressed, on the pads 2a of a first semiconductor element 1a and then the balls are pressed collectively by means of a planarization jig thus forming bumps 4a having arranged height. Three stages of balls 3b are then compression formed on the pads 2b of a second semiconductor element 1b and planarized by compression to form bumps 4b having arranged height. Subsequently, the lead 5a supported on a carrier tape 5b is positioned, at the inner end part 5c thereof, on the bump 4a and connected therewith. The bump 4b is positioned to be superposed on the bump 4a and then they are pressed from the back side, while being heated at a predetermined temperature, and connected through thermocompression. Finally, the gap between the first and second semiconductor elements 1a, 1b is sealed with a resin 6.

7. 发明专利

JPH0448756A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0448756A
公开(公告)日：1992-02-18
申请号：JP15522890
申请日：1990-06-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , KAMATA CHIYOSHI
IPC分类号： H01L23/12 , H01L21/60 , H01L23/49 , H01L23/64
摘要： PURPOSE:To bring the value of characteristic impedance of a bonding wire into coincidence with that of a signal line by disposing a constant potential metallized part near the wire for electrically connecting a semiconductor chip in an IC package to the line. CONSTITUTION:Since a GND metallized part 11a is disposed near a bonding wire 9 in an IC package 1 and an insulator 14 is interposed therebetween, the thickness of the insulator 14 (i.e., a distance between the part 11a and the wire 9) and the material i.e., relative permittivity) of the insulator 14 are suitably selected to bring the value of characteristic impedance of the wire 9 into coincidence with the value (50OMEGA) of the characteristic impedance of a signal line 7. Thus, since reflection of a signal, a waveform distortion in the package 1 are avoided, a high frequency signal can be transmitted without loss.

8. 发明专利

JPH0430544A INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0430544A
公开(公告)日：1992-02-03
申请号：JP13804890
申请日：1990-05-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , KAMATA CHIYOSHI
IPC分类号： H01L21/60 , H01L23/552
摘要： PURPOSE:To reduce crosstalk noise due to input/output signals carried by bump electrodes by providing a conductive member to surround individual bump electrodes on the surface of a chip, and maintain the conductive member at a constant potential. CONSTITUTION:A conductive member 7 is provided between a chip 2 and a printed-circuit board 1, and individual solder bumps 6 on the chip surface are surrounded with a gap by the conductive member 7. The conductive member is connected to an external constant potential source through internal wiring 4, and it shields the individual bumps. The gap between the conductive member and each bump is maintained at vacuum with a low dielectric constant. As a result, it is possible to reduce crosstalk noise due to input/output signals carried by the solder bumps 6. Therefore, the transfer characteristics of input/ output signals are improved, thereby preventing the malfunction of a logic IC on the chip 2.

9. 发明专利

JPS63257292A PIN GRID ARRAY SEMICONDUCTOR DEVICE MOUNTING SPACER 失效
公开(公告)号：JPS63257292A
公开(公告)日：1988-10-25
申请号：JP9087387
申请日：1987-04-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TSUBOI TOSHIHIRO , NISHIUMA MASAHIKO , HONDA ATSUSHI
IPC分类号： H05K1/18

10. 发明专利

JPH08153826A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08153826A
公开(公告)日：1996-06-11
申请号：JP29547694
申请日：1994-11-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , HORIUCHI HITOSHI , KOMATA MAKOTO
IPC分类号： H01L21/60 , H01L23/12 , H01L23/50
摘要： PURPOSE: To provide a high connection reliable LSI package in the case of packaging on a printed-wiring board at low heat resistance fit for multiple pins, high density packaging at low cost. CONSTITUTION: Within the semiconductor integrated circuit device as an LSI package, a TAB tape 6 formed of outer electrode pads 9 comprising a wiring pattern and a part of lead wiring 8 is arranged so that the outer electrodes parts 9 may be positioned on the rear surface side of a substrate 1 while the periphery of the TAB tape 6 may be bent on the main surface side of the substrate 1 so as to electrically connect a semiconductor chip 2 mounted on the main surface of the substrate 1 to one end of the lead wiring 8 provided on the main surface side of the substrate 1.

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