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1. 发明专利

JPH08223503A WIDE ASPECT RATIO TELEVISION RECEIVER 失效
公开(公告)号：JPH08223503A
公开(公告)日：1996-08-30
申请号：JP3041695
申请日：1995-02-20
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： SEKIYA HIROSHI , OKI HIDEAKI , TOMITA HIDEO , IRISAWA HIDEKI
IPC分类号： H04N5/46 , H04N7/015
摘要： PURPOSE: To prevent a video signal from being mis-detected as an identification signal even in the reproduction state of a VTR by controlling the television receiver not only based on a detection result of an EDTV-II identification signal but also based on a detection result of a range of presence/absence of video image. CONSTITUTION: A synchronizing separator circuit 7 separates both horizontal and vertical synchronizing signal from a video signal received from a terminal 1. A gate pulse generating circuit 8 generates a gate pulse for a period of 22H and 285H for which an EDTV-II identification signal is inserted. An output from an LPF clamp circuit 2 is converted into a binary value representing presence/absence of video image by a binarizing circuit 3. An ED identification signal identification circuit 5 discriminates whether or not a video signal is an EDTV-II identification signal based on information of bits 1 to 5 of the EDTV-II identification signal inserted in the video signal. A line detection circuit 9 provides an output of information of a start line when the circuit 9 detects the presence of a video image on a first line in a vertical direction and provides an output of information of an end line when the circuit 9 detects the presence of a video image on a final line to a picture display control circuit 6. The picture display control circuit 6 provides an output of a pattern size switching signal to a deflection circuit 10 based on the discrimination result of an EDTV-II identification signal discrimination information 5 and the video image start/end line information.

2. 发明专利

JPH04322569A WAVEFORM EQUALIZING CIRCUIT 失效
公开(公告)号：JPH04322569A
公开(公告)日：1992-11-12
申请号：JP9030291
申请日：1991-04-22
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： SUZUKI SUNAO , SEKIYA HIROSHI , KURITA TOSHIYUKI , AKIYAMA MORIYOSHI , MURATA TOSHINORI , HISHIYAMA KATSUMI
IPC分类号： H04N5/21
摘要： PURPOSE:To prevent malfunction in a non-steady state and to prevent a video image whose picture quality is deteriorated. CONSTITUTION:A tap coefficient calculated precedingly from a tap coefficient memory 112 is given to a relevant tap of a transversal filter 103 by selecting an output from the tap coefficient memory at a selection circuit 504 in a tap coefficient control circuit 111 at first in 2nd and succeeding time processing. A GCR signal part is extracted from the video signal similarly to the case with first processing to eliminate noise, the result is differentiated through one clock difference and the result is subtracted from an ideal GCR signal waveform to obtain an error signal. The error signal is subject to multiple of -alpha, the result is added to a preceding tap coefficient and stored in the tap coefficient memory 112. The final equalizing waveform is obtained by repeating the waveform equalization for several number of times or for a prescribed time. This circuit is provided with a GCR detection circuit 113 detecting the presence of the GCR signal to prevent the display of a deteriorated video image due to malfunction.

3. 发明专利

JPH02252390A SIGNAL PROCESSING CIRCUIT FOR TELEVISION RECEIVER 失效
公开(公告)号：JPH02252390A
公开(公告)日：1990-10-11
申请号：JP7173189
申请日：1989-03-27
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： KURITA TOSHIYUKI , SEKIYA HIROSHI
IPC分类号： H04N9/79 , H04N9/77 , H04N9/87
摘要： PURPOSE:To quickly decide a standard signal and a non-standard signal by executing processing operation at the time when an input signal is decided not to be a regular signal. CONSTITUTION:If the input signal is the standard signal, the output of a frequency divider 501 and the reset output of the frequency divider 502 nearly coincide with each other in their timing, and the output of the frequency divider 501 comes to be included in the output of the frequency divider 502. A comparator 503 confirms this coincidence by calculating the logical sum of both and so on, and decides it to be the standard signal. However, if the input signal is the non-standard signal, the output of the frequency divider 501 is not included in the output of the frequency divider 502, and the comparator 503 detects discordance, and decides the input signal to be the non-standard signal. In an integrator 127, integration is executed by a program, and if the decision of the non-standard signal results from more than N-times among the decided results of M-times, it outputs a non-standard signal decision level L, and if not so, it outputs a standard signal decision level H.

4. 发明专利

JPH02249392A CLOCK GENERATOR 失效
公开(公告)号：JPH02249392A
公开(公告)日：1990-10-05
申请号：JP6938289
申请日：1989-03-23
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SEKIYA HIROSHI , KURITA TOSHIYUKI , NAKAGAKI NOBUFUMI , MURATA TOSHINORI
IPC分类号： H04N5/06 , H04N5/14 , H04N9/44 , H04N9/77 , H04N11/04 , H04N19/00 , H04N19/102 , H04N19/134
摘要： PURPOSE:To stabilize a synchronizing signal and to attain high picture quality of a video signal by giving a line lock clock to a synchronizing signal generating circuit, a burst lock clock or a line lock clock to a signal processing circuit when a video signal is the standard signal and giving a line lock clock when the video signal is the nonstandard signal. CONSTITUTION:A detection means 6 detects a video signal and in the case of the standard signal only, a phase control means 7 apply phase synchronization of a line lock clock 3 to a burst lock clock 5. When the nonstandard signal is inputted to a signal processing circuit 10, the line lock clock 3 is given and when the standard signal is inputted, the burst lock clock 5 or the line lock clock 3 synchronized with the burst lock clock 5 is given. Moreover, when the nonstandard signal is inputted to a synchronizing signal generating circuit 9, the line lock clock 3 is given and when the standard signal is inputted, the line lock clock 3 synchronized with the burst lock clock 5 is given. Thus, high picture quality and the stable production of synchronizing signal are attained.

5. 发明专利

JPH07264507A WIDE ASPECT TELEVISION DISPLAY DEVICE 失效
公开(公告)号：JPH07264507A
公开(公告)日：1995-10-13
申请号：JP5365594
申请日：1994-03-24
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： SEKIYA HIROSHI , SANO TOSHIMI , FUSHIMI KIYOSHI , NISHISETO TAKAAKI , TOMITA HIDEO
IPC分类号： H04N5/46 , H04N7/01
摘要： PURPOSE:To display images with various aspect ratios on a screen with an aspect ratio of 16:9 by optimum vertical sizes and display positions while saving operation labor. CONSTITUTION:A video signal inputted from an input terminal 1 is processed through a clamping circuit 6 and a filter 8 and then the processed signal is supplied to a binarizing circuit 10 and binarized in accordance with the existence of an image part in each line to judge its aspect ratio. When the aspect ratio is other than 4:3, an image start/end line detecting circuit detects the timing of first and final lines including the image part in each field, a latch circuit 13 latches the count values of a counter 12 at these timing and an arithmetic circuit 14 finds out the vertical width of the image based upon these latched count values. A control circuit 4 controls a deflection circuit 5 based upon the vertical width and the judged result of the circuit 10 so that images are displayed on the screen by optimum vertical sizes and display positions.

6. 发明专利

JPH06296164A TEMPERATURE CONTROL CIRCUIT FOR OPTICAL TRANSMITTER 失效
公开(公告)号：JPH06296164A
公开(公告)日：1994-10-21
申请号：JP8176493
申请日：1993-04-08
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： SEKIYA HIROSHI
IPC分类号： H04B10/293 , H01S5/042 , H04B10/07 , H04B10/40 , H04B10/50 , H04B10/54 , H04B10/564 , H04B10/572 , H04B10/58 , H04B10/60 , H04B10/04 , H01S3/096 , H04B10/06
摘要： PURPOSE:To reduce the time in a temperature control transient state by storing a temperature of a laser diode at drive start and controlling the temperature of the laser diode by using the stored temperature as the set temperature. CONSTITUTION:A FET 5 is closed by a time depending on a time constant of a differentiation circuit comprising a resistor and a capacitor connecting to a gate of the FET 5 at application of power, a voltage generated by a thermister 2 having a resistance in response to a temperature of a laser diode 3 for the case is applied to a capacitor 8, in which charges are stored. The FET 5 is open after lapse of a predetermined time and a temperature of the laser diode 3 at application of power is stored in the capacitor 8 as voltage information. The temperature information is used for a control reference signal to control the temperature of the laser diode 3. Thus, the temperature has only to be controlled only for a change in a temperature rise due to a heat by the operation of the laser diode 3 and the time when a stable state is reached is reduced.

7. 发明专利

JPH0537827A WAVEFORM EQUALIZATION CIRCUIT 失效
公开(公告)号：JPH0537827A
公开(公告)日：1993-02-12
申请号：JP21421191
申请日：1991-08-01
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： NAKAGAKI NOBUFUMI , SUZUKI SUNAO , SEKIYA HIROSHI , KURITA TOSHIYUKI , MURATA TOSHINORI
IPC分类号： H04N5/21
摘要： PURPOSE:To obtain the waveform equalization circuit operated correctly at all times by using a video waveform itself even from a video signal with no reference signal (GCR signal) inserted thereto. CONSTITUTION:The circuit is provided with a GCR detection circuit 113 detecting the presence of a GCR signal and stops waveform equalization using the GCR signal when no GCR signal is in existence to implement waveform equalization using a video waveform. Since the video waveform itself is not a signal whose gain is flat over a wide band different from the GCR signal in general, it is difficult to detect a delay time. Then the operation of a noise elimination circuit 106 is stopped, instead an integration circuit 114 connecting to the post stage of a delay detection circuit 108 is acted to implement integration and distortion information outputted from the delay detection circuit 108 is outputted. Thus, when it is discriminated that the GCR signal is not inserted by the GCR detection circuit 113, waveform equalization using the video waveform is implemented.

8. 发明专利

JPH04123579A TELEVISION RECEIVER 失效
公开(公告)号：JPH04123579A
公开(公告)日：1992-04-23
申请号：JP24241390
申请日：1990-09-14
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： KURITA TOSHIYUKI , SEKIYA HIROSHI , SUZUKI SUNAO , AKIYAMA MORIYOSHI
IPC分类号： H04N5/14 , H04N9/00 , H04N9/64
摘要： PURPOSE:To exclude disturbance such as dot crawl by bringing the processing state of a 3-dimension processing circuit into the nonstandard processing state by an output of a detection circuit detecting the end of operation of a waveform equalizing circuit. CONSTITUTION:An operation end detection circuit 106 detects the operation end of a waveform equalizing circuit 105 to control an output of the waveform equalizing circuit 105 via a switch circuit 107. Moreover, a standard signal/ nonstandard signal detection circuit 109 receives an output of the switch circuit 107 to discriminate whether the output of the switch circuit 107 is a standard signal or a non-standard signal and when the result of discrimination tells the standard signal, a 3-dimension processing circuit 108 is controlled to implement the standard signal processing and when the signal is non-standard signal, the 3-dimension processing circuit 108 is processed in the non-standard signal state. Then the output of the 3-dimension processing circuit 108 passes through a video amplifier circuit 110 and is outputted on a cathode ray tube 112, on which the signal is displayed as a picture. Thus, production of disturbance such as dot crawl is avoided.

9. 发明专利

JPS63193783A N-FOLD SCAN TELEVISION RECEIVER 失效
公开(公告)号：JPS63193783A
公开(公告)日：1988-08-11
申请号：JP2458587
申请日：1987-02-06
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SEKIYA HIROSHI , MURATA TOSHINORI , KURITA TOSHIYUKI , ARAI IKUYA , NAKAGAWA HIMIO
IPC分类号： H04N7/01 , G09G1/04 , G09G1/16 , G09G5/12
摘要： PURPOSE:To improve a phase error answer when a normal horizontal synchronizing signal is inputted by constituting a two-fold horizontal synchronism generation circuit and a two-fold horizontal deflection circuit in one phase locked loop circuit. CONSTITUTION:A phase locked loop circuit 9 consists of a phase comparator 13, a low pass filter 14, a voltage controlled oscillator 15 and a 1/2 frequency divider 19. A 1/910 frequency divider 18 is provided before the phase synchronous circuit 9, and it always operates the phase comparator 13 with a normal horizontal synchronizing frequency. If the normal horizontal synchronizing signal is selected as an input signal, the normal horizontal synchronizing signal is inputted to the phase comparator 13. If an n-fold horizontal synchronizing signal is selected, the horizontal synchronizing signal whose frequency has become the same as the normal horizontal synchronizing signal by the 1/910-frequency divider is inputted to the phase comparator 13. For switching a standard signal and the two-fold signal as the input signal, the phase synchronous circuit of horizontal synchronism can be constituted in one stage, whereby the same phase error answer can be obtained. If the normal signal is inputted, the phase error answer can considerably be improved.

10. 发明专利

JPH03231585A SIGNAL PROCESSING UNIT 失效
公开(公告)号：JPH03231585A
公开(公告)日：1991-10-15
申请号：JP2594490
申请日：1990-02-07
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： MURATA TOSHINORI , KURITA TOSHIYUKI , NAKAGAKI NOBUFUMI , SEKIYA HIROSHI , SUZUKI SUNAO
IPC分类号： H04N7/01 , H04N11/20
摘要： PURPOSE:To form a noise reduction circuit of frame cyclic type by reading a 1st field memory at a normal speed and writing a signal of a 3rd input field to a same address as readout. CONSTITUTION:When a 1st switch 2 connects an input terminal to a 1st field memory 3 to write an input signal, an input terminal written precedingly is read from a same address going to be written in a 1st field memory 3 prior to the write as one frame delay signal at a same speed as the write speed and a 1-frame delay signal to be read is extracted via a 3rd switch 12 and it is used together with a current input signal to be written in the 1st field memory 2 to apply calculation processing. Thus, the 1st and 3rd input field information sets are obtained simultaneously to obtain information of one frame difference simultaneously.

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