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1. 发明专利

JP2002222600A TEST METHOD FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002222600A
公开(公告)日：2002-08-09
申请号：JP2001016482
申请日：2001-01-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： OSHIMA NAOMI , HAYASHI HIDEKI , KOBA TAKASHI , HIGETA KEIICHI
IPC分类号： G01R31/28 , G01R31/3183 , G06F12/16 , G11C29/00 , G11C29/10 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To provide a test method for a semiconductor device in which re- designing of a test data generating circuit is not required to correspond to the row/column constitution to be tested and which can be applied easily to the other product. SOLUTION: This device is a semiconductor device comprising a test pattern generator 4 testing simultaneously RAM(A) 1, RAM(B) 2, RAM(C) 3 having different row/column constitution. The test pattern generator 4 is constituted of a RAM test control circuit 5, a write-enable generating circuit 6, a row address generating circuit 7, a column address generating circuit 8, a data generating circuit 9, or the like. Each signal line of row/column addresses corresponding to each RAM is connected respectively. Row/column addresses are shifted from the minimum value to the maximum value in order and test data is supplied commonly. Thus, data retention test by a checker board pattern is realized.

2. 发明专利

JP2002243801A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2002243801A
公开(公告)日：2002-08-28
申请号：JP2001041080
申请日：2001-02-19
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HAYASHI HIDEKI , HIGETA KEIICHI , NAKAHARA SHIGERU , KOBA TAKASHI , OSHIMA NAOMI
IPC分类号： G01R31/28 , G06F12/16 , G11C29/00 , G11C29/02
摘要： PROBLEM TO BE SOLVED: To provide a self-test technique capable of providing a circuit for storing failure addresses detected by a self-test circuit of a built-in memory, avoiding the operation of the circuit from being interrupted every time failure is detected, and outputting accurate failure information in real time. SOLUTION: A multiplying circuit (120) for multiplying a clock signal (ϕ0) supplied from an external tester, etc., is provided. The self-test circuit inside a chip is operated by the multiplied clock signal (ϕ1). Serial-parallel conversion is performed on the results of determination by the self-test circuit to output the converted results.

3. 发明专利

JP2000091906A EXCLUSIVE OR CIRCUIT 失效
公开(公告)号：JP2000091906A
公开(公告)日：2000-03-31
申请号：JP26268698
申请日：1998-09-17
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KANETANI KAZUO , NANBU HIROAKI , YAMAZAKI SU , OHATA KENICHI , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI , HIGETA KEIICHI , YAMAGUCHI KUNIHIKO , KOBA TAKASHI
IPC分类号： H03K19/21
摘要： PROBLEM TO BE SOLVED: To make the XOR circuit fast by providing an OR circuit constituted by connecting bases of respective transistors to a 1st node point and a 2nd node point, respectively, connecting their emitters to a 3rd node in common, and connecting a current source to the 3rd node point. SOLUTION: Currents are so defined that Iab=Icd, Iab>=Iy, and OUT('1')> VBB1>OUT('0'). When '0' (even) is obtained as an XOR output, the currents Iab and Icd are made to flow to one of resistances R10 and R20 mutually. Since VBB1>OUT('0'), a current (Iab+Icd+Iy) flows to a resistance R3. Then '0' is obtained as the XOR output through an OR circuit W1. When '1' an odd number is obtained as the XOR output, both the currents Iab and Icd flow concentrically to one of the resistances R10 and R20 and do not flow to the other. Then '1' is obtained as the XOR output through the OR circuit W1.

4. 发明专利

JPH11355128A EXCLUSIVE OR CIRCUIT 失效
公开(公告)号：JPH11355128A
公开(公告)日：1999-12-24
申请号：JP15713698
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI ULSI SYS CO LTD
发明人： KANETANI KAZUO , NANBU HIROAKI , YAMAZAKI SU , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI , KOBA TAKASHI
IPC分类号： H03K19/21
摘要： PROBLEM TO BE SOLVED: To hold the amplitude of the output of an exclusive OR circuit to a regular level, to reduce signal amplitude generated in load resistance and to speed up an exclusive OR circuit by connecting first and second current supply circuits controlled by the output of the exclusive OR circuit respectively to output nodes. SOLUTION: A current supply circuit Y1 is composed of a transistor Q11 where the output OUT of a four inputs exclusive OR circuit XOR is received by a base and an emitter is connected to a current source Iab2 and a transistor Q12 where reference voltage VBB1 is received by a base, an emitter is connected to a current source Iab2 and a collector is connected to an output node N1. Although a current supply circuit Y2 has the same constitution as Y1, a collector being a current supply part is connected to an output node N2. The values of resistances R10 and R20 are set to be lower than the values of former resistances R1 and R2 so that low potential L equal to a former circuit can be obtained in the output node when the currents Iab and Iab2 flow in the resistance R10, for example.

5. 发明专利

JPH09147571A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH09147571A
公开(公告)日：1997-06-06
申请号：JP32501995
申请日：1995-11-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MAKUTA KIICHI , NOJIRI TATSUO , KOBA TAKASHI , FUKAZAWA TAKESHI
IPC分类号： G11C11/41 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To prevent the time from the memory cell selection operation to the sense amplifier activation from becoming excessively short when the gate length (the width dimension of polysilicon wiring layer) of the MOS transistor changes by the variation of the manufacturing process. SOLUTION: A sense amplifier activation control signal ϕsa is activated in synchronization with the completion of the pulsive change of an address change detection pulse signal ϕatd. Fuse blowing judgment circuits 15-18 determine the pulse width of the address change detection pulse signal ϕatd and the period until the sense amplifier activation control signal ϕsa is possible from the completion of the pulse change of the signal according to the fuse program state. Fuse blowing judging circuits 15-18 is programmed according to the measurement result using a circuit 30 where the drain/source current of the MOS transistor can be monitored from the outside of the chip.

6. 发明专利

JPH07282596A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH07282596A
公开(公告)日：1995-10-27
申请号：JP6744294
申请日：1994-04-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IIDA HARUHITO , MORITA SADAYUKI , KOBA TAKASHI , AOTO TOSHIRO , MAKIKO TAKAO , ISHIBASHI KOICHIRO , KOMIYAJI KUNIHIRO
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04
摘要： PURPOSE:To attain the reducing of memory chip size by increasing the utilizing ratio of a relief address storage circuit provided with fuse elements and reducing the chip occupancy area of a redundant circuit. CONSTITUTION:A program circuit 1 storing the addresses of defective parts generated in a memory is provided with relief address storage circuits capable of storing selectively an X system address and a Y system address. Which address of the X system or the Y system the storage circuit 11 is storing is discriminated by the melted-cut states of respective fuse elements c, d of an X system activating fuse circuit 12 and a Y system activating fuse circuit 14. Since both of the X system address and the Y system address can be stored in the relief address storage circuit 11. when the prescribed number of defection reliefs (word lines or bit lines) are wanted, it is sufficient to prepare relief address storage circuits 11 of the same number as that of defection reliefs. Thus, the utilizing ratio of the relief address storage circuit is increased and effective utilization of the chip area is attained.

7. 发明专利

JP2010186557A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2010186557A
公开(公告)日：2010-08-26
申请号：JP2010100794
申请日：2010-04-26
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NISHIYAMA MASAHIKO , HIGETA KEIICHI , KOBA TAKASHI
IPC分类号： G11C15/04
摘要： PROBLEM TO BE SOLVED: To reduce power consumption and variation of current consumption.
SOLUTION: In a semiconductor memory device which includes a CAM part (4) which can hold entry data, which compares the entry data with input comparison data, and which can output the comparison result, the device is provided with a controller (10) for generating retrieving request for the CAM part. The controller includes a retrieving rate setting means which can set a retrieving rate of a level at which variation of current is suppressed. The retrieving rate setting means can set a retrieving rate of a level at which variation of current is suppressed, a current by retrieving operation can be made to flow always by performing such setting, variation of current can be suppressed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：降低功耗和电流消耗的变化。解决方案：在包括可以保存输入数据的CAM部分（4）的半导体存储器件中，其将输入数据与输入比较数据进行比较，并且可以输出比较结果，该器件设置有控制器 10）用于产生针对CAM部件的检索请求。控制器包括检索率设置装置，其可以设置抑制电流变化的电平的检索率。检索率设定装置可以设定电流变化被抑制的电平的检索率，通过进行这种设定可以总是进行检索操作的电流，可以抑制电流的变化。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2006120186A Semiconductor integrated circuit and picture processing system 审中-公开
标题翻译：半导体集成电路和图像处理系统
公开(公告)号：JP2006120186A
公开(公告)日：2006-05-11
申请号：JP2004303648
申请日：2004-10-19
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KOBA TAKASHI , ANAMI NAOYUKI , SAKAI MIKIKO , PARK SERYUNG , HIGETA KEIICHI
IPC分类号： G11C15/04
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C15/00
摘要： PROBLEM TO BE SOLVED: To provide a circuit system in which throughput can be improved by avoiding providing system clocks of two systems and operation restriction that it must be synchronized to a slow system clock when an operation frequency of an associative memory is slower than an operation frequency of a system LSI.
SOLUTION: A clock control circuit (103) down-converting an internal clock (Φ1) of LSI (101) is provided and a control system operating an associative memory circuit (102) using a slowed control signal is provided.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种电路系统，其中可以通过避免提供两个系统的系统时钟和操作限制来提高吞吐量，并且当相关存储器的操作频率较慢时必须与慢系统时钟同步而不是系统LSI的工作频率。解决方案：提供对LSI（101）的内部时钟（Φ1）进行下变频的时钟控制电路（103），并且提供使用减慢的控制信号来操作关联存储器电路（102）的控制系统。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005228461A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2005228461A
公开(公告)日：2005-08-25
申请号：JP2004265297
申请日：2004-09-13
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NISHIYAMA MASAHIKO , HIGETA KEIICHI , KOBA TAKASHI
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04 , G11C15/00
摘要： PROBLEM TO BE SOLVED: To improve the throughput of a CAM (content addressable memory) by reducing power consumption and current consumption fluctuations. SOLUTION: This device has a control circuit 409 for taking in a comparison result between the partial bit of entry data and the corresponding bit of comparison data is taken in, and inhibiting comparison between the remaining bit of the entry data and the corresponding bit of the comparison data when the comparison result shows noncoincidence. The inhibition of comparison between the remaining bit of the entry data and the corresponding bit of the comparison data reduces the number of signal lines activated during one cycle of the comparison operation, and thus power consumption is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过降低功耗和电流消耗波动来提高CAM（内容可寻址存储器）的吞吐量。解决方案：该装置具有用于获取进入数据的部分比特和比较数据的对应比特之间的比较结果的控制电路409，并且禁止输入数据的剩余比特与相应的比较比较数据比较结果显示不一致。禁止比较数据的剩余比特与比较数据的对应比特之间的比较减少了比较操作的一个周期期间激活的信号线的数量，从而降低了功耗。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JPH08315595A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH08315595A
公开(公告)日：1996-11-29
申请号：JP13739495
申请日：1995-05-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MAKIKO TAKAO , MORITA SADAYUKI , KOBA TAKASHI , KINOSHITA YOSHITAKA
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
摘要： PURPOSE: To obtain a semiconductor memory in which increase of chip area due to a redundancy memory mat can be suppressed as much as possible. CONSTITUTION: With regard to memory array MRY0, MRY1 provided for every input circuit I/O0-I/O3, I/O4-I/O7, redundancy memory mat RMAT0, RMAT1 can replace a memory mat to be repaired existing in any one of a plurality of memory arrays MRY0, MRY1 having different I/O circuit. More specifically, the plurality of memory mat arrays share the redundancy memory mat. With such arrangement, chip area being occupied by redundancy memory mat can be reduced.

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