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1. 发明专利

JPH05216448A TEST METHOD AND TEST DEVICE FOR FRAME MEMORY 失效
公开(公告)号：JPH05216448A
公开(公告)日：1993-08-27
申请号：JP1916892
申请日：1992-02-04
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： KAWAMATA WATARU , SUEOKA MAMORU , NISHIDA TAKEHIKO , SUZUKI KUNIO , YOKOYAMA MASAHIRO
IPC分类号： G06F11/22 , G06F12/16 , G09G5/00 , G09G5/36 , G09G5/397 , G09G5/399 , G11C29/00 , G11C29/04 , G11C29/56
摘要： PURPOSE:To provide a test method and a test device for a frame memory which can automatically execute a test of a frame memory composing a frame memory of double buffer system in the quite same conditions as the actual operations without depending on visual confirmation or the like. CONSTITUTION:When a frame memory 101 of one of a double buffer system is tested, the other frame memory 102 is used as a test buffer, display data outputted from a SAM 107 of a VRAM 103 of n pieces which composes the frame memory 101 in the same conditions as the actual operation is inputted to a SAM 108 of a VRAM 104 of n pieces which composes the frame memory 102, contents of the frame memory 101 is compared with contents of the frame memory 102, and information about malfunction parts of the VRAM 103 of n pieces which composes the frame memory 101 is collected.

2. 发明专利

JPS62243052A BUS SWITCHING DEVICE IN MULTI-COMPUTER SYSTEM 失效
公开(公告)号：JPS62243052A
公开(公告)日：1987-10-23
申请号：JP8594786
申请日：1986-04-16
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： SUZUKI KUNIO , NAKAMICHI SHUICHI , TAKAMATSU RYOICHI , SUZUKI MASAHIRO
IPC分类号： G06F15/16 , G06F13/00 , G06F13/14 , G06F13/20 , G06F13/36 , G06F15/173 , G06F15/177
摘要： PURPOSE:To fix the monitor time for detecting an abnormality against no- response of an I/O, by providing a control means which does not monitor the time, when a CPU is in a state that a bus connection to the I/O is being kept waiting by a switching device. CONSTITUTION:In case when a request of a start is supplied to a host adaptor side, when a switching device 105 scans the host adaptor 103 and turns off a BUSY signal 26-0, a start signal SEL 27-0 is outputted. When the signal 27-0 goes to an L level, a signal 18 goes to an H level through a gate 47, and a signal 21 which is selected by a selector 6 goes to an H level. As a result, an FF 10 is reset and its output Q goes to an L level, and suppresses a gate 2, therefore, a counter 3 is not updated thereafter, and the scan stops. In such a way, the time required for receiving the BUSY signal as a response from a controller, after the host adaptor has outputted the signal 27-0 is only a delay of a gate delay, and the response monitor time of the host adaptor side can be fixed.

3. 发明专利

JPS6380315A TERMINAL EQUIPMENT 失效
公开(公告)号：JPS6380315A
公开(公告)日：1988-04-11
申请号：JP22485486
申请日：1986-09-25
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： SUZUKI KUNIO , ONO FUMIAKI , MATSUBARA HIROSHI
IPC分类号： G06F3/023 , H03M11/10 , H03M11/12
摘要： PURPOSE:To eliminate the need of an exclusive key by supervising the input time interval of a code corresponding to an extended key and a code inputted next when the code corresponding to the extended key is inputted and treating the interval as a command signifying a terminal exclusive function when the interval is a prescribed value or below and as a code string outputted to a host device when the interval is over the prescribed value. CONSTITUTION:A key input interruption program is started by the key input of a keyboard 12 to fetch a data, thereby discriminating whether or not the data is a code corresponding to the extended key, and the timer set is confirmed when the code is not the extended code. When the timer is not set, it is regarded as the input by a character code key, the input processing program is started and the result is transferred to a central processing unit 15. When the fetched data is the extended code, a prescribed time is set to the timer, the extended code is stored to confirm it and the keyboard input processing program is started similarly as above.

4. 发明专利

JPH09149061A COMMUNICATION CONTROLLER, COMMUNICATION NETWORK AND ITS CONTENTION CONTROL METHOD 失效
公开(公告)号：JPH09149061A
公开(公告)日：1997-06-06
申请号：JP30451795
申请日：1995-11-22
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： UCHIYAMA TOSHIHIKO , SATOU YUKIHIRO , SATO HIDEYA , SUZUKI KUNIO , KUMAGAI NOBUHIRO , ONUKI TAKESHI , MARUYAMA HISAYUKI , NAKANO YOSHIHIRO , KONO KAZUO
IPC分类号： G06F13/00 , H04L12/40 , H04L12/42 , H04L12/423
摘要： PROBLEM TO BE SOLVED: To control only one master to be processed without contention even when plural masters are erroneously in existence on the same line. SOLUTION: Each control station 1 has a master function 21 so as to be a master by a command from a host computer 2. A station 1 being a master station publicates and broadcasts a master notice including its own priority at a prescribed period. On the other hand, a control station 1 receiving the master notice, when its own status indicates a master, compares the priority of master notice with its own priority and becomes a slave when its own priority is lower.

5. 发明专利

JPH02125314A CIRCUIT DEVICE, CIRCUIT NETWORK, AND LIVE WIRE INSERTING AND PULLING-OUT METHOD FOR CIRCUIT DEVICE 失效
公开(公告)号：JPH02125314A
公开(公告)日：1990-05-14
申请号：JP17811489
申请日：1989-07-12
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： MUTO KOJI , OKADA MASAKAZU , YAMAGUCHI SHOJI , SUZUKI KUNIO
IPC分类号： G06F1/18 , G06F3/00 , G06F13/40
摘要： PURPOSE:To eliminate a trouble accompanied with insertion and pulling-out of live wires by connecting the output driver of a circuit device in the non-feed state to a communication bus and generating a signal to prevent signal transmission to the communication bus from the circuit device and supplying power from a power source to the output driver to eliminate the signal. CONSTITUTION:When a certain circuit device 2 will be inserted, a signal to supply power to an output driver 21 of the circuit device 2 to be inserted is generated after the other circuit devices in the feed state are prevented from transmitting signals to the communication bus of a bus network. This generated signal is kept till stabilization of the output driver 21 and is eliminated thereafter. At the time of pulling-out of the circuit device, a prescribed signal is supplied to the bus network from the circuit device 2 to be pulled out to stop signal transmission of the other circuit devices. This signal is kept till stabilization of the output driver 21, and the circuit device 2 is eliminated thereafter. Thus, disturbance during insertion or pulling-out of the circuit device is prevented.

6. 发明专利

JPS6390067A FLOPPY DISK CONTROL CIRCUIT 失效
公开(公告)号：JPS6390067A
公开(公告)日：1988-04-20
申请号：JP23318686
申请日：1986-10-02
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： SUZUKI KUNIO , NAKAMICHI SHUICHI
IPC分类号： G11B20/10
摘要： PURPOSE:To omit retry processing by forming a floppy disk control (FDC) circuit to be added to an FDC LSI. CONSTITUTION:When a motor signal 1 is turned on, a dummy ready signal 6 and an FDC ready signal 8 are kept to ON state only the time determined by a resistor 15 and a capacitor 16. After the passage of the time, the signal 6 is turned off and a ready signal 10 is converted into an FDC ready signal 8. When the signal 1 is turned off, the signal 6 is turned on, so that the signal 8 is turned on. During the ON of the signal 6, a signal 11 is kept to OFF state by an inverter 5 and an AND gate 13 is kept at a closed state, so that an index signal 12 is masked and is not inputted to an FDC and the FDC can be prevented from reading unfixed data and ending its operation by a read error during the period. Thus, retry processing can be omitted by forming the additional circuit 17.

7. 发明专利

JPH08152942A ELECTRONIC COMPUTER SYSTEM 失效
公开(公告)号：JPH08152942A
公开(公告)日：1996-06-11
申请号：JP29423294
申请日：1994-11-29
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： UEDA SHINICHI , YAMAGUCHI SHOJI , SUENAGA MASASHI , WATANABE HIROSHI , FURUYA MASAYOSHI , YOKOYAMA KAZUHARU , SUZUKI KUNIO , SHIMIZU HISHIYUKI , OTANI KOICHI
IPC分类号： G06F1/26 , G06F1/00
摘要： PURPOSE: To perform the protection of a computer and the improvement of operability for turning on/off a power source including a peripheral device easily with an existent computer when it is possible for the computer to relax or get out of the conditions for continuing its operation. CONSTITUTION: A CPU 2 equipped with a means for inputting a power source ON/OFF command from an uninterruptible power supply(UPS) and a means for outputting the stop command signal of the UPS 60 at the time of completely turning off the power source of this CPU 2, a fan 4 for cooling, and a control circuit 10 for turning on/off the power source of the CPU 2 and a peripheral device 3 corresponding to the output of a stop sensor for the fan 4 and a command from the outside or an operator, is housed in a housing 1. When the fan 4 is stopped, the control circuit 10 shuts down the CPU 2 and when the CPU 2 is completely shut down, the power source of the peripheral device 3 is turned off.

8. 发明专利

JPH06214900A BUS SWITCHING DEVICE 失效
公开(公告)号：JPH06214900A
公开(公告)日：1994-08-05
申请号：JP780193
申请日：1993-01-20
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： ISHIKURA HIDEJI , MORIOKA TAKAYUKI , MASUI KOJI , SUZUKI KUNIO
IPC分类号： G06F11/20 , G06F13/00 , G06F13/36
摘要： PURPOSE:To prevent another device from being affected in the case of exchanging a device of which bus is abnormal by providing a gate control circuit for monitoring the states of respective buses and controlling the disconnection of any bus showing the abnormal state. CONSTITUTION:When input/output controllers A1 and B1 desives to execute the READ/WRITE of data with a magnetic disk, the acquisition of the bus is tried by respective arbitrations when the bus can be acquired, either a magnetic disk A3 or a magnetic disk B4 is selected by selection, and a READ/ WRITE command is sent by information communication. Although the bus switching device is controlled by a gate control circuit 15, the state of an SCSI bus signal of each device to be changed is monitored by a signal 12 and when the device with the bus signal abnormal is detected, that device is disconnected by a signal 14. Therefore, the other device to start the input/output operation is not affected.

9. 发明专利

JPH0321992A GRAPHIC DISPLAY CONTROL METHOD AND DISPLAY DEVICE FOR COMPUTER 失效
公开(公告)号：JPH0321992A
公开(公告)日：1991-01-30
申请号：JP15468289
申请日：1989-06-19
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： NISHIKAWA ATSUHIKO , SHIMIZU KAZUYOSHI , MORIOKA TAKAYUKI , SUZUKI KUNIO , MASUI KOJI
IPC分类号： G06F3/153 , G09G5/00 , G09G5/36 , G09G5/377
摘要： PURPOSE:To improve response performance and to alter man-machine processing without altering software by putting a host computer side in charge of only input/output processing for plant information without performing data processing regarding graphic drawing on a graphic display on the host computer side at all. CONSTITUTION:A host computer 22, process input/output mechanisms 25 and 26, and a graphic display 23 are connected to a network 24 and the host computer 22 has a data base 21. The graphic display 23 is provided with a processing function for a screen display except the real-time data base 21 and when plant information which varies in real time is necessary, the host computer 22 is requested; when real-time information is sent, it is converted into graphic data, which is displayed together with other data. Consequently, a large-scale process control system has a good response and the software cost of man- machine interface is reducible.

10. 发明专利

JP2002005969A VOLTAGE INPUT MONITORING DEVICE 失效
公开(公告)号：JP2002005969A
公开(公告)日：2002-01-09
申请号：JP2000180425
申请日：2000-06-15
申请人： HITACHI LTD , HITACHI INF & CONTROL SYST
发明人： KATSUYAMA ICHIRO , SUZUKI KUNIO , NAGAYAMA SHUICHI , DOKEN TOMOHIKO
IPC分类号： G01R19/165
摘要： PROBLEM TO BE SOLVED: To provide a voltage input monitoring device allowing precise detection of a primary side resistor voltage impression state by means of a secondary side resistor without respect to an ambient temperature fluctuation. SOLUTION: A voltage ON state of the primary side resistor 2 is detected by determining a resistance value changing rate of the secondary side resistor 3 in a heating time. An impression voltage OFF state to the primary side resistor 2 is detected by comparing and determining an actual resistance value after a lapse of a predetermined time.

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