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1. 发明专利

JPH07262007A INFORMATION PROCESSOR 失效
公开(公告)号：JPH07262007A
公开(公告)日：1995-10-13
申请号：JP4597794
申请日：1994-03-16
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： HAKAMATA MASASHI , HIRAOKA TORU , OSHIMA KAZUO
IPC分类号： G06F9/38 , G06F9/30
摘要： PURPOSE:To process two instructions at maximum in one cycle by-replacing the combination of two instructions decided in advance with one compound instruction equivalent to these two instructions. CONSTITUTION:A CLI instruction is extracted from an IBR 10 by a first instruction extraction shifter 20 and stored in an IRP 30. On the other hand, a BC instruction is stored in an IRS by a second instruction extraction shifter 40. A replace instruction generating circuit 90 generates the CLI-BC compound instruction by detecting that the combination of those CLI and BC instructions has been stored in the IRP 30 and the IRS 50. That CLI-BC compound instruction is processed on the respective stages of a pipeline as one instruction. Thus, the insertion of an instruction following two instructions to the pipeline can be made faster by one cycle, and the processing speed can be accelerated.

2. 发明专利

JP2001014160A INFORMATION PROCESSOR 失效
公开(公告)号：JP2001014160A
公开(公告)日：2001-01-19
申请号：JP18837299
申请日：1999-07-02
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HIRAOKA TORU , ITOI TOMONAGA , HAKAMATA MASASHI
IPC分类号： G06F9/38 , G06F9/30
摘要： PROBLEM TO BE SOLVED: To advance a pipeline processing by reducing delay due to a branch- destination instruction read by requesting a memory to read the branch- destination instruction of a branch instruction to an instruction buffer when the branch instruction is decoded. SOLUTION: At an IF stage, instructions set in BIRP 400 and BIRS 500 are decoded by a 1st instruction decoder 900. When a branch instruction is decoded by the 1st instruction decoder 900, an instruction read request for a branch-desntination instruction is issued to an instruction cache 100. The instructions set in the BIRP 400 and BIRS 500 are stored in IFR 100, and the instruction set in the BIRP 400 is transferred to a selecting circuit 1010. Thus, two instructions are decoded in every machine cycle at the IF stage as a 1st instruction decoding stage and transferred to a D stage as a 2nd instruction decoding stage. At the 2nd instruction decoding stage, the instructions set in IRP 1200 and IRS 1300 are decoded by a 2nd instruction decoder 1700.

3. 发明专利

JP2002342074A INFORMATION PROCESSOR 失效
公开(公告)号：JP2002342074A
公开(公告)日：2002-11-29
申请号：JP2001150267
申请日：2001-05-21
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YOSHIHIRA KENJI , HIRAOKA TORU , HAKAMATA MASASHI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To easily mount instruction segmentation control from an instruction buffer register to an instruction register and to effectively utilize the capacity of the instruction buffer register in a pipeline type information processor. SOLUTION: A means for transferring instruction data from a second instruction register to a first instruction register is provided. Further, independently of an instruction validity identification means corresponding to the first instruction register, the instruction validity identification means corresponding to the second instruction register is provided. By combining them and a simultaneous decoding analysis means and using them, the instruction segmentation control from the instruction buffer register to the instruction register is performed at a timing delayed for one cycle stage compared to a conventional technique and mounting is easily realized.

4. 发明专利

JPH10283184A DATA PROCESSOR 失效
公开(公告)号：JPH10283184A
公开(公告)日：1998-10-23
申请号：JP9254297
申请日：1997-04-10
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： HIRAOKA TORU , ITOI TOMONAGA , HAKAMATA MASASHI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To advance the read processing of a succeeding condition branching instruction even in the case that the condition branching instruction continues by starting the processing of the next instruction before judging and deciding the branching establishment and branching non-establishment of the condition branching instruction by a branching judgement circuit corresponding to a predicted result. SOLUTION: This data processor is provided with first - forth non-prediction side instruction address saving registers 940 - 970 for saving the address of the instruction of the non-prediction side of the condition branching instruction selected in a selection circuit 930 or the like. Then, the instruction address of the instruction of the non- prediction side is saved at the time of decoding the condition branching instruction, and in the case that all streams are in a using state and the condition branching instruction is decoded, the stream on a not-taken side is opened when the condition branching instruction is the prediction of being taken and the stream on a taken side is opened when it is the prediction of being not taken. Then, the opened stream is secured as the stream for reading the branching instruction destination of the succeeding condition branching instruction and the read processing of the branching destination instruction is advanced.

5. 发明专利

JPH09274566A INFORMATION PROCESSOR 失效
公开(公告)号：JPH09274566A
公开(公告)日：1997-10-21
申请号：JP8393096
申请日：1996-04-05
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY , HITACHI MICROCOMPUTER SYST
发明人： INOUE TSUKASA , HIRAOKA TORU , NAKATANI AKIHIRO , HAKAMATA MASASHI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To accelerate the pipeline processing speed of an instruction sequence including a branching instruction by simultaneously executing pipeline information from the instruction next to the branching instruction and the pipeline processing of a branching destination instruction when the branching instruction is inputted to a pipeline. SOLUTION: Two kinds of processing on the D stage of the pipeline are simultaneously executed by a 1st instruction register 15 provided with a decoder, 2nd instruction register 16, 1st branching instruction detection circuit 18 and 2nd branching instruction detection circuit 19. A 1st selector 17 selects the instruction to be supplied to an address adder 6 for operand and an address adder 12 for instruction, and a 2nd selector 20 selects information showing the state of mask field of a conditional branching instruction to be supplied to a branch discrimination circuit 10. Besides, a 3rd selector 21 selects a branching instruction detecting signal to be supplied to an instruction sequence selection circuit 11 and the address adder 12 for instruction. The 1st selector 17, 2nd selector 20 and 3rd selector 21 are controlled by an output 11A of the instruction sequence selection circuit 11.

6. 发明专利

JPH08227360A INFORMATION PROCESSOR 失效
公开(公告)号：JPH08227360A
公开(公告)日：1996-09-03
申请号：JP3256195
申请日：1995-02-21
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , HITACHI COMPUTER ENG
发明人： HAKAMATA MASASHI , HIRAOKA TORU , MORI SHIGERU , YAMAMOTO MICHITAKA , ITOI TOMONAGA
IPC分类号： G06F9/38 , G06F9/30
摘要： PURPOSE: To advance the detection timing of a word overlap and to reduce overhead caused by the detection of a word overlap in an information processor for executing processing followed by the detection of a word overlap. CONSTITUTION: In addition to a 1st word overlap detector 150, a 2nd word overlap detector 110 for detecting a word overlap by using only the contents of a D1 field 104, a D2 field 106 and an L field 102 when the base address register numbers of 1st and 2nd operands specified by B1 and B2 fields are mutually equal is also prepared. The preceding processing of decoding for a succeeding instruction group under pipeline control is temporarily suppressed by a 2nd word overlap detection signal 111. Thereby the detection timing of a word overlap is advanced and overhead for instruction rereading which is caused by the cancel of a succeeding instruction in a conventional method is removed, so that the processing speed of the information processor can easily be improved.

7. 发明专利

JP2009110385A Data processing system 有权
标题翻译：数据处理系统
公开(公告)号：JP2009110385A
公开(公告)日：2009-05-21
申请号：JP2007283523
申请日：2007-10-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYAMOTO SHOJI , HAKAMATA MASASHI , FUKAO KAZUICHI , MURAKAMI SHOKI
IPC分类号： G06F9/30 , G06F1/04 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a data processing system, which controls processing performance with reasonable accuracy by controlling the processing performance of data processing with hardware. SOLUTION: The data processing system having a data processing section 110 includes: a first register 121 for measuring processing performance of data processing and storing the measured performance value as the result; a second register 122 for storing a target performance value which is target predetermined processing performance: a performance comparison section 123 for comparing the measured performance value stored in the first register 121 and a target performance value stored in the second register 122; and a performance adjustment section 124 for adjusting processing performance of data processing according to the comparison result by the performance comparison section 123. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种数据处理系统，通过控制硬件数据处理的处理性能，以合理的精度控制处理性能。具有数据处理部分110的数据处理系统包括：第一寄存器121，用于测量数据处理的处理性能并存储测量的性能值作为结果; 用于存储作为目标预定处理性能的目标性能值的第二寄存器122：用于比较存储在第一寄存器121中的测量性能值和存储在第二寄存器122中的目标性能值的性能比较部123; 以及性能调整部分124，用于根据性能比较部分123的比较结果来调整数据处理的处理性能。版权所有：（C）2009，JPO＆INPIT

8. 发明专利

JP2000227857A INFORMATION PROCESSOR FOR BRANCH DESTINATION ASSOCIATIVE STORAGE SYSTEM 失效
公开(公告)号：JP2000227857A
公开(公告)日：2000-08-15
申请号：JP2894199
申请日：1999-02-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TAMURA TERUHITO , HIRAOKA TORU , OSHIMA KAZUO , ITOI TOMONAGA , HAKAMATA MASASHI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide accurate branch prediction by performing an appropriate amount of registration/deletion by independently performing the registration/ deletion to/from first and second branch destination associative memories. SOLUTION: This device is provided with means 15-1 and 15-2 for respectively and independently holding the results of reference to a first low-speed large- capacity branch destination associative memory 12 and a second high-speed small-capacity branch destination associative memory 13 for storing, respectively, the instruction address and branch destination address of a branching instruction according to the execution history of branching instructions in the past, means 17-1 and 17-2 for respectively and independently discriminating branch establishment/non-establishment according to held predictive information and means 18-1 and 18-2 for respectively and independently performing the registration/deletion to/from the first and second branch destination associative memories 12 and 13 according to the discriminated result.

9. 发明专利

JP2009094782A Semiconductor system 审中-公开
标题翻译：半导体系统
公开(公告)号：JP2009094782A
公开(公告)日：2009-04-30
申请号：JP2007263262
申请日：2007-10-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKEDA GENICHI , FUKAO KAZUICHI , HAKAMATA MASASHI , MURAOKA SATOSHI
IPC分类号： H03K19/0175 , H03K19/003 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To avoid the occurrence of a fault by precisely predicting the signal quality degradation in a high-speed transmission line during operation of a device.
SOLUTION: An output adjustment value of an adjustment value control logic which outputs the most suitable impedance adjustment value in accordance with the impedance variance of a buffer due to temperature changes during operation of the device is collated with an already set impedance adjustment value, and the collation result is used as a prediction report to control the use of a line including the related buffer, thereby avoiding the occurrence of a fault in the line.
COPYRIGHT: (C)2009,JPO&INPIT

10. 发明专利

JP2001236223A INFORMATION PROCESSOR 失效
公开(公告)号：JP2001236223A
公开(公告)日：2001-08-31
申请号：JP2000044722
申请日：2000-02-22
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HIRAOKA TORU , ITOI TOMONAGA , HAKAMATA MASASHI , TANAKA SHINICHI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To improve a processing speed by advancing the decoding of a following instruction when address inter-lock is generated. SOLUTION: An address queue is arranged between an instruction decoding stage and an address adding stage. Thus, even when address interlock is generated, the decoding of the following instruction can be realized. When the instruction refers to a memory device, the decoded information of the instruction is stored in both the address queue and an instruction queue, and when the instruction does not refer to the memory device, the decoded information of the instruction is stored only in the instruction queue. Thus, when the instruction does not refer to the memory device, the execution of a pipe line stage necessary for referring to the memory device can be reduced, and the pipe line stage can be omitted. Therefore, it is possible for the following instruction to early refer to the memory device. As a result, it is possible to shield pipe line overhead due to the address interlock of the following instruction, and to improve the processing speed of the instruction.

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