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1. 发明专利

JPH06243188A DELAY TIME CORRECTING SYSTEM 失效
公开(公告)号：JPH06243188A
公开(公告)日：1994-09-02
申请号：JP2560893
申请日：1993-02-15
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： IWATA HIDENOBU , MATSUMOTO TAKASHI , YOSHINO RYOZO , HIYAMA TORU , KAWASHIMA MASATOSHI
IPC分类号： G06F17/50 , G06F15/60
摘要： PURPOSE:To correct a path delay time after the end of layout and wiring of cells without changing already prepared wiring information at the time of LSI design. CONSTITUTION:Delay time correcting circuits DLY0 to DLY3 resolve the delay time differences brought about by inter-cell wiring length between FFs FF0 to FF3 and FFs FF4 to FF7. If it is necessary to correct the delay times of DLY0 to DLY3 after the end of layout and wiring of cells at the time of LSI design, cells for delay time correction which are preliminarily prepared and have the same size and pin arrangement as circuits DLY0 to DLY3 and are different by delay times are substituted for circuits DLY0 to DLY3 to correct the delay times.

2. 发明专利

JPS63204593A METHOD FOR ACCESSING DYNAMIC MEMORY 失效
公开(公告)号：JPS63204593A
公开(公告)日：1988-08-24
申请号：JP3462887
申请日：1987-02-19
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： YOSHINO RYOZO , OGAWA YOSHIYUKI , MATSUMOTO TAKASHI
IPC分类号： G11C11/406 , G11C11/34
摘要： PURPOSE:To remove a memory access queuing time due to refreshing operation by refreshing the final memory access cycle in a refresh available cycles set up to several times the bank period of a memory access cycle with priority and executing the memory access of other cycles with priority. CONSTITUTION:Dynamic memories 6, 7 are memory banks for respective memory devices and execute memory accessing operation or refreshing operation based on a refresh request signal from AND gates 14, 15 or a memory access request signal from AND gates 12, 13. The refreshing operation is executed with priority in the final memory access cycle out of the refresh available cycles and the memory accessing operation is executed with priority in the other cycles. Banks other than a bank executing the memory accessing operation is capable of executing the refreshing operation. Consequently, the probability of waiting can be reduced even at the time of memory access based on a random address or continuous addresses.

3. 发明专利

JPS62166622A DA CONVERTER 失效
公开(公告)号：JPS62166622A
公开(公告)日：1987-07-23
申请号：JP793986
申请日：1986-01-20
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： YOSHINO RYOZO , YAMAZAKI SHOJI , MATSUMOTO TAKASHI
IPC分类号： H03M1/74
摘要： PURPOSE:To form a DA converter and its control logic on the same LSI to reduce the mounting area of the device, by arranging the basic circuit of the DA converter in such a way that the switch of each digit is radially dispersed from the center of the mounting area of the DA converter and reducing the influence of the wiring resistance between each switch. CONSTITUTION:A DA converter is formed by using a basic circuit composed of two collector resistances 1, two transistors 2 and 3, and one current source 4 as a switching circuit. This basic circuit is used as the switching circuit which is turned on or turned off when a digital input signal is higher or lower in level than a reference voltage Vref. When this DA converter is constituted of 63 pieces of switching circuits and those which are simultaneously turned on of the switching circuits are arranged collectively, influences of wiring resistances are apt to be received when switches which are weighted by 2 only are turned on. Therefore, concentration of electric currents is prevented by radially arranging the switching circuits in the order of weighting from the smallest one.

4. 发明专利

JPH04196810A DIFFERENTIAL PULSE WIDTH RESTORATION CIRCUIT 失效
公开(公告)号：JPH04196810A
公开(公告)日：1992-07-16
申请号：JP32316290
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： MATSUMOTO TAKASHI , IWATA HIDENOBU
IPC分类号： H03K5/04 , H03K3/02
摘要： PURPOSE:To allow any input pulse to have the same pulse width by connecting the output of a differential amplifier with the reset terminal of a differential R-S flip flop, and making the delay time of the differential amplifier to be longer than that of the differential amplifier of a differential differentiation circuit. CONSTITUTION:Inputs C and D are connected with the A and A' of a differential amplifier circuit 2, and a differential amplifier 1. The inputs C and D passing through the amplifier 1 are turned into E and F after delayed by an X time, and respectively inverted and connected with the B' and B. The outputs G and H of the circuit 2 are obtained after differentiating the C and D. This circuit 2 is used as the differential differentiation circuit, the outputs G and H are connected with the S and S' of a differential R-S flip flop 4, and the rising time of outputs L and M is decided. Moreover, the outputs L and M of the flip 4 are connected with a differential amplifier 3, delayed by only a Y time longer than the X time, the outputs J and K of the amplifier 3 are connected with the R and R' of the flip 4, the outputs L and M of the flip 4 are reset, and the rising time of the pulse is decided. Thus, the pulses of the outputs L and M having the always constant pulse width for the Y time can be obtained.

5. 发明专利

JPS63307371A SWITCH CIRCUIT 失效
公开(公告)号：JPS63307371A
公开(公告)日：1988-12-15
申请号：JP14295387
申请日：1987-06-08
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： YOSHINO RYOZO , KOSAKA TAIJI , MATSUMOTO TAKASHI
IPC分类号： G01R31/28
摘要： PURPOSE:To improve the reliability of a switch circuit by holding an output voltage much lower than the low output level of a front-stage differential switch circuit under the control of a power source side, and turning off the switch circuit regardless of the input of a rear-stage differential switch circuit to which the varied output is inputted. CONSTITUTION:When an IC 20 to be tested is in an input state, a control differential switch circuit 4 in an IC tester output driver 1 is held off. Namely, a high-level base voltage VB5 is applied to a transistor(TR) Q5 and a low-level base voltage VB6 is applied to a TR Q6, which is held off, so that the high level of the front-stage differential switch circuit 2 is determined by the base voltage VB1 to a TR Q1. In this state, pulse voltages are inputted as the voltage VB1 and the base voltage VB2 to a TR Q2 and then the waveform voltage of the VB2 is inputted to the IC 20 as it is, i.e. as a voltage Vi. The voltages VB1 and VB2 are therefore transmitted at a high speed and the operation measurement of the IC in a fast operation state is performed with high accuracy, thereby improving the reliability.

6. 发明专利

JPS63232621A SWITCHING CIRCUIT 失效
公开(公告)号：JPS63232621A
公开(公告)日：1988-09-28
申请号：JP6395087
申请日：1987-03-20
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： YOSHINO RYOZO , KOSAKA TAIJI , MATSUMOTO TAKASHI
IPC分类号： H03K19/086 , H03K17/60 , H03K19/00
摘要： PURPOSE:To forcibly bring an output at normal operation to a high level by providing a transistor (TR) whose emitter is connected to an emitter coupling part in a differential switching circuit and controlling the base voltage of the TR so as to turn off two TRs of the differential switching circuit forcibly. CONSTITUTION:In bringing the base voltage VB3 of a TR Q3 to a voltage higher than the voltage VB2 in a switching time slower than the normal time before the changeover of the base voltage VB4 of the TR Q4 as shown in time-chart in figure, the TR Q3 is turned on gradually, while the TR Q2 is turned off gradually. Thus, the current I2 flowing to the Tr Q2 is switched to the TR Q3 and the output voltage V0 of an IC (DUT)2 to be tested depends on the switching time of the VB3 and clamped to a high level. In bringing the voltage VB3 to the low level, the high level clamp is released. Since the TRs of the differential switching circuit of the emitter coupling are turned off for both polarities in this way, the output level is fixed to the high level regardless of the input of the differential switching circuit.

7. 发明专利

JPH06273483A CONNECTION DEVICE FOR IC TESTER 失效
公开(公告)号：JPH06273483A
公开(公告)日：1994-09-30
申请号：JP5748893
申请日：1993-03-17
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： KOSAKA TAIJI , YOSHINO RYOZO , MATSUMOTO TAKASHI
IPC分类号： G01R31/26 , H01L21/66
摘要： PURPOSE:To achieve signal transmission between IC testers with a light and compact shape by providing a step-shaped connection part between a test head and a test board, connecting the IC tester to one end, and then burying a connection pin in the other end. CONSTITUTION:When a test head 11 is fitted to a test board 10, the exposed part of the substrate edge part of a wiring pattern A 12a comes in contact with a signal SC pin A 16a. Further, with a wiring pattern B 12b, the exposed part of the substrate contacts the signal SC pin B 16b and ground pads 15a and 15e contact a ground SC pin 17. On the other hand, the IC to be measured which is mounted to the board 10 is connected to the IC side end part in contact structure, thus electrically connecting the IC to be measured which is mounted to the board 10 and an IC luster via the head 11. Therefore, since the head 11 and the board 10 are connected by the SC pin, the mounting area does not increase even if the number of transmission signals increases, the shape is made smaller, and a coaxial connector, a probe, and a fixing plate can be eliminated, thus drastically reducing weight.

8. 发明专利

JPH05223898A IC TESTER 失效
公开(公告)号：JPH05223898A
公开(公告)日：1993-09-03
申请号：JP2510492
申请日：1992-02-12
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： IWATA HIDENOBU , MATSUMOTO TAKASHI , ISHIMARU HIROYUKI
IPC分类号： G01R31/28 , G01R31/3183
摘要： PURPOSE:To accomplish data delay processing for the speed of an element, exceeding its operating speed. CONSTITUTION:The test data string of data rate (x) is emitted by IC tester 2 ALPG 21 to an LSI 1 and a correction latch circuit 24. The correction latch circuit 24 separates the test data string by a separatorapart and distributes to four systems of delay circuits. Each system of delay circuit delays the partial test data string, which was separated and whose data rate has become x/4, by the use of operation clocks and passes it to a multifold part. The multifold part time divides the outputs of the four systems of delay circuits and turns them multifold, restores the test data of the data rate (x), and passes it to a comparator circuit 25. The comparator circuit 25 compares this with the output data from the LSI and outputs a judgement.

9. 发明专利

JPH04189051A TRANSMISSION WAVEFORM CORRECTION CIRCUIT 失效
公开(公告)号：JPH04189051A
公开(公告)日：1992-07-07
申请号：JP31884490
申请日：1990-11-22
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： KOSAKA TAIJI , YOSHINO RYOZO , MATSUMOTO TAKASHI
IPC分类号： G01R31/319 , G01R31/28 , H03K19/086 , H04L25/03
摘要： PURPOSE:To conduct the test of an IC with high accuracy by allowing an IC tester to correct the attenuation of a signal through a transmission line between the IC tester and a DUT. CONSTITUTION:When a collector voltage VC2 changes from a low level to a high level, since a signal with overshoot is inputted to bases of transistors (TRs) Q4, Q3, a TR Q2 is turned on. Through the operation, a capacitor C3 is released and the voltage across the capacitor is subtracted from a driver output voltage. As a result, an unsharpened pulse waveform with overshoot/ undershoot on a transmission line 50 is corrected and the resulting signal is inputted to a DUT.

10. 发明专利

JPH04193429A AUTOMATIC ATTACHMENT FITTING DEVICE 失效
公开(公告)号：JPH04193429A
公开(公告)日：1992-07-13
申请号：JP32316190
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： MATSUMOTO TAKASHI , MORIYAMA EIJI , KOSAKA TAIJI
IPC分类号： B23P19/06 , H05K7/12
摘要： PURPOSE:To reduce the number of parts on the fitting side and uniformly tighten bolts in a short time by fitting an attachment with bolts having torque controlled motors. CONSTITUTION:A torque controlled motor 6 is fitted to a bolt 4 of a PK tester 1. At fitting an attachment 3, the bolts 4 are rotated, it can be automatically fitted, and when the thread of bolts are fully screwed and defined torque are applied on the controlled motors 6, rotation is automatically stopped. When '1' is input to the ON part of a motor control part 12, it passes through an inverter to be inverted to '0'. Then a coil 13 is supplied current and a second relay 9 connected to +P.S is short-circuited. A third relay 10 is short-circuited to the +P.S side, the torque controlled motor fitted to the bolt 4 is normally rotated, and the attachment 3 can be automatically fitted.

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