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1. 发明专利

JPH06289846A MOVING IMAGE OUTPUT DEVICE 失效
公开(公告)号：JPH06289846A
公开(公告)日：1994-10-18
申请号：JP8045193
申请日：1993-04-07
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST , HITACHI COMPUTER ELECTRONIC
发明人： YOSHIDA NAOMI , DOI KIYOTAKA , TAKAGI TSUTOMU , WASHITANI NOBUHIRO , MASUYAMA KANJI , AKIBA SHIGETOSHI , YOSHIKAWA NAOMI , ABE HITOSHI , TAJIMA KATSUTOSHI , IWAI MASAHIRO
IPC分类号： G06F3/153 , G09G5/36 , H04N5/907 , H04N5/93 , H04N5/937
摘要： PURPOSE:To obtain the moving image output device which obtains a natural moving image even if processes for inputting image data and writing them in image memories are slightly delayed by providing a memory switching control circuit. CONSTITUTION:When a transfer start signal is inputted from a computer 2, a memory switching control circuit 9 monitors the frame blanking signal outputted from a read control circuit 6 and outputs a transfer request signal for image data to a computer 2 at the moment the frame blanking signal varies from a low level to a high level. Consequently, even if the processes for inputting the image data and writing them in the image memories 4 and 5 are slightly delayed, the natural moving image can be obtained by switching the image memories 4 and 5 where the data are read and written on condition that writing ends between the beginning of the blanking period wherein the request to transfer the image data is made to the ending of the next blanking period.

2. 发明专利

JPH05334235A 失效
公开(公告)号：JPH05334235A
公开(公告)日：1993-12-17
申请号：JP14443292
申请日：1992-06-04
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST , HITACHI COMPUTER ELECTRONIC
发明人： NARA KAZUHISA , MASUKO ATSUSHI , HORIGUCHI HARUKO , IWAI MASAHIRO , SEKIGUCHI MASAYORI
IPC分类号： G06F13/28
摘要： PURPOSE:To attain the transfer of data along a bank between a main memory and a bank memory by a DMA transfer without operating the switching of the bank. CONSTITUTION:At the time of the reading or writing of data at the time of a DMA trasfer, signals 18a-18c obtained by decoding the upper bit of an address outputted from a decoder 4 are used as the chip select signals 20a-20c of main memories 7a-7c, and the outputs 19a-19d of a bank switching register 5 are used as the chip select signals 21a-21d of bank memories 8a-8d by a selector 6. And also, on the other hand, the signals 18a-18c obtained by decoding the upper bit of the address outputted from the decoder 4 are used as the chip select signals 21a-21d of the bank memories 8a-8d. Thus, the bank memories can be allocated to a memory space once, and the data transfer along the bank memory can be executed without operating the switching of the bank.

3. 发明专利

JPH07306665A SIMPLIFIED POWER MANAGEMENT SYSTEM FOR DISPLAY DEVICE 失效
公开(公告)号：JPH07306665A
公开(公告)日：1995-11-21
申请号：JP10045694
申请日：1994-05-16
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： OSHIMA TOSHIYOSHI , IWAI MASAHIRO , KOGOORI FUMIHIRO , IWATA KENICHI
IPC分类号： G09G5/00
摘要： PURPOSE:To realize the simplified power saving of a display device by controlling an image/synchronizing signal and power supply to the display device from the outside on a host device and the display device without power management function, and contribute to the reduction of carbon dioxide, sulfur dioxide, nitrogen dioxide dis charged in large quantities from an electric power plant through the realization of power saving in addition to reducing the cost of electric power and the purhcase expanses of new hardware and software for users. CONSTITUTION:A power management system for a host device 9 and a display device 6 existing without power management function can realize simplified power saving by monitoring a keyboard and mouse signals S1, S2 from the outside so as to control an image/synchronizing signal S5 and power supply S6 to the display device 6. In this power management system, a synchronous separating/synthesizing circuit that can cope with a composite signal system, one of signal systems for the display device is provided at a synchronizing signal output circuit 5, at the input part from the host device 9 and at the output part to the display device 6, and the unused state of the host device 9 can be shifted to three kinds of power-saving modes easily by the optionally set elapsed time.

4. 发明专利

JPH066213A LOCK DETECTING CIRCUIT FOR PLL CIRCUIT 失效
公开(公告)号：JPH066213A
公开(公告)日：1994-01-14
申请号：JP16308792
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST , HITACHI COMPUTER ELECTRONIC
发明人： WASHITANI NOBUHIRO , YOSHIDA NAOMI , TANIMOTO MASAYASU , TAJIMA KATSUTOSHI , ABE HITOSHI , IWAI MASAHIRO
IPC分类号： H03L7/095
摘要： PURPOSE:To provide a PLL lock detecting circuit capable of detecting the lock with high accuracy even with a small phase difference obtained between a reference signal and a comparison signal. CONSTITUTION:An EOR circuit 1 secures an exclusive OR between a reference signal 1a and a comparison signal 1b and detects a phase difference. The detected signal 1c and both signals 1a and 1b are defined as the data and the clocks and then inputted to 1st and 2nd D flip-flop circuits 2 and 3 respectively. These circuits 2 and 3 hold the data at the trailing edge of the clock, therefore only the fall phase difference between the signals 1a and 1b is detected. Then the output signals 2c and 3c are inputted to a NOR circuit 4. Thus a locking signal 4c is outputted so that a locking state and an unlocking state are secured when the fall phase are matched with each other and not matched with each other between both signals 1a and 1b respectively.

5. 发明专利

JPH052494A INTERRUPTION CONTROL SYSTEM 失效
公开(公告)号：JPH052494A
公开(公告)日：1993-01-08
申请号：JP15438091
申请日：1991-06-26
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST , HITACHI COMPUTER ELECTRONIC
发明人： HORIGUCHI HARUKO , MASUKO ATSUSHI , TAKAGI TSUTOMU , NARA KAZUHISA , IWAI MASAHIRO , TOMIMATSU KAZUFUMI , ABE HITOSHI
IPC分类号： G06F9/48 , G06F9/46 , G06F13/14
摘要： PURPOSE:To connect a circuit having an interruption response function to an extended slot without an interruption response signal. CONSTITUTION:An interruption requesting signal 18 of a circuit 15A having an interruption response function is inputted through an extended slot 14 to a personal computer main body 1 and the output of an address decoder 11A and the AND of an IO read-signal 7 are returned as an interruption response to the circuit 15A. In short, by reading a special address, the interruption response signal is inputted to the circuit 15A. By reading the special address at the beginning of the processing in the interruption routine, the circuit 15A is operated in the sequence of the interruption request, the interruption response and the inherent interruption processing. Then, when the constitution is not obtained, since there is not the means to input the interruption response signal to the circuit 15A, the processing of the interruption response cannot be performed, there is the possibility of the malfunction, and this can be evaded by the interruption control system.

6. 发明专利

JPH04181292A DISPLAY SIGNAL CONTROL SYSTEM 失效
公开(公告)号：JPH04181292A
公开(公告)日：1992-06-29
申请号：JP30892190
申请日：1990-11-16
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： OSHIMA TOSHIYOSHI , TOMIMATSU KAZUFUMI , IWAI MASAHIRO , HIROTA TAMOTSU , YAGINUMA ATSUSHI
IPC分类号： G09G5/00 , G09G5/12 , G09G5/18
摘要： PURPOSE:To allow the display optimum for a display by sending the frequency mode with which a discrimination signal output circuit provided on the display can deal to a host device. CONSTITUTION:The frequency mode of the display is outputted from the discrimination signal output circuit 2 in the display device 1 to a microprocessor 4 of the host device 3. The microprocessor 4 receiving the signal decides a dot clock and horizontal and vertical deflection frequencies as the frequency mode of the display. This information is calculated by equation 1, equation 2 indicating the number of the horizontal and vertical dots which can be displayed on a screen. The information is then transmitted as a signal S1 to a program control circuit 5. The program control circuit 5 forms a timing chart for display. The use of the display device of the single frequency mode for all the host system devices 3 is possible and the display is made always at the center of the screen without adjustment.

7. 发明专利

JPH0612022A LIQUID CRYSTAL FILTER FOR CRT DISPLAY 失效
公开(公告)号：JPH0612022A
公开(公告)日：1994-01-21
申请号：JP16725192
申请日：1992-06-25
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： IWAI MASAHIRO , SEKIGUCHI MASAYORI , OSHIMA TOSHIYOSHI
IPC分类号： G02B5/20 , G02F1/13 , G09F9/00 , G09G1/00 , H01J29/89
摘要： PURPOSE:To obtain the filter effect suitable for an ambient environment by sticking and mounting a thin panel of a liquid crystal on the front surface of a cathode ray tube of a CRT display and utilizing the liquid crystal contrast effect obtd. by controlling the polarization angles of the axial direction possessed by the liquid crystal molecules. CONSTITUTION:The thin panel 8 of the liquid crystal is stuck on the surface of a glass valve 7 which is the cathode ray tube surface of the CRT display 6 and the effect of preventing the flicker from the CRT display 6 is obtd. by utilizing the contrast effect possessed by the liquid crystal itself by controlling the polarization angles of the axial direction of the liquid crystal molecules 9. Namely, the emitted light quantity 14 from the CRT display 6 and the light quantity 13 from the outside are controlled by moving the polarization angles of the respective liquid crystal molecules 9 thereby decreasing the quantity of the light to be passed. The filter effect meeting the ambient environment is obtd. if the polarization angles are automatically set by a circuit section 10 for controlling the polarization angles of the liquid crystal by providing a photodetecting sensor 11 for measuring the brightness of the external light on the outside.

8. 发明专利

JPH03195180A PICTURE SIGNAL CONVERTER 失效
公开(公告)号：JPH03195180A
公开(公告)日：1991-08-26
申请号：JP33282589
申请日：1989-12-25
申请人： HITACHI LTD , HITACHI VIDEO ENG , HITACHI COMPUTER ELECTRONIC
发明人： WASHITANI NOBUHIRO , TAKAGI TSUTOMU , TAKAI KATSUHIKO , ABE HITOSHI , SEKIGUCHI MASAYORI , IWAI MASAHIRO
IPC分类号： H04N5/04 , H03M1/66 , H04N5/06 , H04N5/067
摘要： PURPOSE:To obtain an analog picture signal, to which a synchronizing signal with high accuracy is added, without requiring the processing circuit of the analog signal by inputting the synchronizing signal and a digital picture signal to a D/A converter. CONSTITUTION:Digital picture signals 1a-1d of four bits are outputted from a picture signal generator 4. These digital picture signals are inputted to the high-order 4 bits of a D/A converter 1 of 6 bits and the synchronizing signal from a synchronizing signal generation part 2 is inputted to the low-order 2 bits. In such a way, by using the D/A converter 1 to handle the data of plural bits which number of bits is larger than the number of bits in the digital picture signal, the synchronizing signal is connected to the arbitrary bit position including the low-order bit and the digital picture signal and the synchronizing signal are simultaneously converted to analog signals by using one D/A converter 1. Thus, without using a synchronizing signal, adding circuit, the synchronizing signal can be added to the analog picture signal with high accuracy.

9. 发明专利

JPH0537969A MONITORING SYSTEM FOR ERROR OF IMAGE DATA 失效
公开(公告)号：JPH0537969A
公开(公告)日：1993-02-12
申请号：JP21306191
申请日：1991-07-31
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST , HITACHI COMPUTER ELECTRONIC
发明人： AKIBA SHIGETOSHI , YOSHIDA NAOMI , TAKAGI TSUTOMU , TANIMOTO MASAYASU , ABE HITOSHI , TAJIMA KATSUTOSHI , IWAI MASAHIRO
IPC分类号： G06F11/00 , G06F12/16 , G09G5/00 , H03M13/00 , H04N1/21 , H04N17/04
摘要： PURPOSE:To judge the deterioration of picture quality due to the generation of an error by judging a memory generating a fault without unnecessarily stopping system operation. CONSTITUTION:Errors in output data from memories 1 to 4 are detected by respective data error detecting circuits 5 to 8 and the numbers of generated errors are counted up by respective counter circuits 9 to 12, 18. The circuit 18 is reset in each output of data corresponding to one picture and the circuits 9 to 12 are reset at a period longer than the resetting period of the circuit 18. Thereby the value of the circuit 18 indicates the number of errors in one screen and the values of the circuits 9 to 12 indicate the repeated generation frequency of errors in the outputs of respective memories 1 to 4 within the reset period. When the data of respective inner registers in respective memory error reporting circuits 13 to 16 and a frame error reporting circuit 19 coincide with the values of the counters, respective circuits 13 to 16, 19 report the failure of the memories and the deterioration of picture quality to a central processing circuit 53.

10. 发明专利

JPH04184622A METHOD AND DEVICE FOR CONTROLLING DISPLAY 失效
公开(公告)号：JPH04184622A
公开(公告)日：1992-07-01
申请号：JP31562090
申请日：1990-11-20
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： IWAI MASAHIRO , OSHIMA TOSHIYOSHI , TOMIMATSU KAZUFUMI , YAGINUMA ATSUSHI , HIROTA TAMOTSU
IPC分类号： G06F3/153
摘要： PURPOSE:To automatically adjust a screen to its optimum position and optimum size by adding the identification signal indicating the frequency and the timing of the synchronous signal outputted to a display device from each CPU to the flyback time of the synchronous signal and detecting the identification signal. CONSTITUTION:A signal S5 selected optionally by a switcher 8 by the control of a system control part 5 included in a computer 1 is separated into a synchro nous signal S1 and a video signal S2 by the switcher 8. The signal S2 is directly transferred to a display device 2. In regard of the signal S1 consisting of the horizontal and vertical synchronizing signals outputted from a CPU 6 or 7, a specific identification signal that identifies a CPU is added to the flyback time of the signal S1 by an adding circuit 3. When a signal S6 is inputted, a control circuit 4 takes out an identification signal S5 added in the computer 1 and converts the input synchronizing signal into a signal S7 that can secure the optimum display of the screen position based on the information of the signal S5. The signal S7 is outputted to a deflecting circuit 12. Thus the opti mum display is ensured to both CPU 6 and 7.

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