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1. 发明专利

JPS63116250A MEMORY CONTROL CIRCUIT 失效
公开(公告)号：JPS63116250A
公开(公告)日：1988-05-20
申请号：JP26351686
申请日：1986-11-05
申请人： HITACHI LTD
发明人： KOBAYASHI SHIGEO , TANABE KANJI , HONMA SADAJI , YAMADA NOBUO
IPC分类号： G06F1/30 , G06F1/00 , G06F1/26 , G06F12/16
摘要： PURPOSE:To restrict the influence of a miswriting only to a specific address by outputting the specific address from an address switching part during the detection of OFF of a main power supply by a main power supply OFF detecting part. CONSTITUTION:When the main power supply 1 is OFF, a VCC-OFF signal outputted from a main power supply OFF detecting part 31 is turned to an H level. Thereby the address outputs A0-AN of an address switching part 32,a chip select signal CS from a data holding control part 33 and a memory writing signal W are respectively turned to the H levels respectively through OR circuits 32A, 32B, 33A, 33B. During the OFF of the main power supply, an address output to a memory 4 is fixed on the H level. Thus, the area of the memory 4 can be utilized at an optional ratio by selecting the number of OR circuits constituting an address switching part 32.

2. 发明专利

JPS6154550A Integration circuit device 失效
标题翻译：集成电路设备
公开(公告)号：JPS6154550A
公开(公告)日：1986-03-18
申请号：JP17489284
申请日：1984-08-24
申请人： Hitachi Ltd
发明人： TAMURA SHIGEAKI , YAMADA NOBUO
IPC分类号： G11C29/00 , G06F11/22 , G06F12/16 , G11C29/12
摘要： PURPOSE: To simplify the test of a RAM by integrating the RAM and a logical circuit on a chip, connecting a self-test circuit of the RAM to the RAM via a connection switch circuit by the external designation of a test mode and outputting the test result to outside.
CONSTITUTION: A self-test circuit 5 supplies a write-enable signal, the address signal and the write data to a RAM2 and compares this write data with the read data of the RAM2. When the test mode signal is applied to an input terminal 4-3, selectors 7-1W7-3 switch the connection of the RAM2 to the circuit 5 from a logical circuit part 3. Then a test is carried out synchronously with the clock sent from an input terminal 4-1. The result of this test is outputted through an output terminal 4-2.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了通过将RAM和逻辑电路集成在芯片上来简化RAM的测试，通过外部指定测试模式，通过连接开关电路将RAM的自检电路连接到RAM，并输出测试结果到外面。构成：自检电路5将写入使能信号，地址信号和写入数据提供给RAM2，并将该写入数据与RAM2的读取数据进行比较。当测试模式信号被施加到输入端子4-3时，选择器7-1-7-3从逻辑电路部分3将RAM2的连接切换到电路5.然后与时钟同步地进行测试从输入端子4-1发送。该测试的结果通过输出端子4-2输出。

3. 发明专利

JPS55163852A CONNECTING SYSTEM 失效
公开(公告)号：JPS55163852A
公开(公告)日：1980-12-20
申请号：JP6988879
申请日：1979-06-06
申请人： HITACHI LTD
发明人： YAMADA NOBUO
IPC分类号： H01L21/60
摘要： PURPOSE:To suppress expansion of a solder bump for connecting due to surface tension and eliminate the improper connection by a method of connecting between semiconductor substrates by providing a substrate interval controlling solder bump separately from the solder bump with a size larger than the solder bump on a first substrate. CONSTITUTION:There are formed an evaporated film 4 mounted with a connecting solder bump 5 on the condutor 3 on the surface of the silicon chip 1 of first substrate 20 and a substrate interval controlling solder bump 11 through an evaporated film 10 on a conductor 9, and a protective film 2 on the other surface of a chip 1. A printed conductor 6 and a glass dam 7 are formed on the ceramic plate 8 of second substrate 30, connecting solder bump 5 is inserted between the substrates 20 and 30, and are dissolved and connected. Since the amount of the solder bump 11 is large, the interval between both the substrates is controlled to eliminate expansion of the solder bump 5 at the center.

4. 发明专利

JPS5242033A MEMORY UNIT 失效
公开(公告)号：JPS5242033A
公开(公告)日：1977-04-01
申请号：JP11653575
申请日：1975-09-29
申请人： HITACHI LTD
发明人： YOSHINO RIYOUZOU , YAMADA NOBUO
IPC分类号： G06F12/06 , G06F12/00 , G06F13/00 , G11C7/00
摘要： PURPOSE:The number of components used and man-power required are reduced by controlling the cases that input data is put in to memory unit as it is by the selection signal of memory card and that input data is inversed and put in to memory unit.

5. 发明专利

JPH04276395A RANDOM ACCESS MEMORY 失效
公开(公告)号：JPH04276395A
公开(公告)日：1992-10-01
申请号：JP3585291
申请日：1991-03-01
申请人： HITACHI LTD
发明人： YAMADA NOBUO
IPC分类号： G11C29/00 , G11C29/42
摘要： PURPOSE:To properly use parity data by external input and parity data by internal generation by building in a parity generator circuit, a memory for parity and a parity control circuit. CONSTITUTION:At the time of a writing cycle, the inputted data are written and simultaneously, the parity data are generated by a parity generator part 4. Here, for the parity data, according to the input level of a parity control input terminal PC, either of the data generated by the parity generator part 4 or the external data inputted from a data terminal D8 is selected by a parity control circuit 5 and written into a memory part 3 for parity. Thus, by switching the parity control signal, it can be switched whether the data of the parity generator part are used or the input data from the external part are used, and thus, two using methods can be performed by the same RAM.

6. 发明专利

JPH01151094A SEMICONDUCTOR MEMORY ELEMENT 失效
公开(公告)号：JPH01151094A
公开(公告)日：1989-06-13
申请号：JP30960887
申请日：1987-12-09
申请人： HITACHI LTD
发明人： YAMADA NOBUO
IPC分类号： G11C11/401 , G11C11/34 , G11C11/413
摘要： PURPOSE:To execute a writing cycle at a high speed by latching the writing data impressed from an external part to a writing data input terminal toward a data latch circuit at the time of the writing cycle. CONSTITUTION:In a writing cycle, the writing data impressed to I/O terminals I/O1-I/O4 are latched to a data latch 3 and the latched data are made into the writing data written to a memory cell 2. Consequently, after the said data are latched, the level of the I/O terminal may be changed, the writing data defined time necessary to write in a memory cell satisfies the set-up and holding time necessary to latch the data latch, and then, even when the said semiconductor element is in the writing condition, the level of an input/output terminal can be changed. Thus, the collision of the input/output data at the time of the change to a next cycle can be easily avoided and the writing cycle can be shortened.

7. 发明专利

JPS63142408A VOLTAGE MONITOR CIRCUIT 失效
公开(公告)号：JPS63142408A
公开(公告)日：1988-06-14
申请号：JP28880286
申请日：1986-12-05
申请人： HITACHI LTD
发明人： TAKAHASHI SHIGEKAZU , YAMADA NOBUO , YOSHINO RYOZO
IPC分类号： G06F1/28 , G06F1/00 , G06F12/16 , H02J9/00 , H02J9/06
摘要： PURPOSE:To prevent the malfunction by connecting a level shift output circuit to the output of a voltage monitor IC and shifting the level more than noise voltage. CONSTITUTION:A voltage monitor circuit consists of a main power feeder 1, a voltage monitor IC 2, a transistor TR 5, a level shift diode 6, a bias resistance 7, a NAND gate 9, a power switching circuit 11, an auxiliary power source 12, and a memory 13. The feeder 1 is connected to the voltage monitor IC 2, the power switching circuit 11, etc., and the output of the switching circuit 11 is connected to the memory 13, the NAND gate 9, etc. Since the output of the voltage monitor IC 2 is taken out from the connection point between the level shift diode 6 and the bias resistance 7, the noise voltage is not transmitted to the output to prevent the malfunction of the NAND gate 9.

8. 发明专利

JPS62264494A MEMORY DEVICE 失效
公开(公告)号：JPS62264494A
公开(公告)日：1987-11-17
申请号：JP10698486
申请日：1986-05-10
申请人： HITACHI LTD
发明人： YAMADA NOBUO
IPC分类号： G11C7/00
摘要： PURPOSE:To unify the consumption electric current of a memory by arranging logically the memory element of a selecting condition and the same number of the memory element of a nonselecting condition in a pair and keeping always constantly the ratio of the number of a memory element to come to be the selecting condition and the number of the memory element to come to be the nonselecting condition. CONSTITUTION:Even when memory selecting signals SEL1-SEL3, a chip signal CHIP and a writing signal W are combined by any polarity, the half number of the memory element group out of memory element groups comes to be a selecting condition and the remaining half number comes to be a nonselecting condition. Namely, when either of memory blocks 31-34 is selected by memory selecting signals SEL1-SEL3 and any of them is not selected, memory elements MO1-MOn or M11-M1n of the half number of the memory element group constituting the memory block are the selecting condition and the remaining half number of them is nonselecting condition. Thus, the ratio of the memory element of the action condition and the nonaction condition can be constantly kept, the consumption electric current of the memory device can be constantly kept and the electric power source variation can be suppressed.

9. 发明专利

JPS62124693A SEMICONDUCTOR MEMORY ELEMENT 失效
公开(公告)号：JPS62124693A
公开(公告)日：1987-06-05
申请号：JP26240485
申请日：1985-11-25
申请人： HITACHI LTD
发明人： YAMADA NOBUO
IPC分类号： H01L27/10 , G11C11/34
摘要： PURPOSE:To provide an internal circuit that eliminates the indefinite time of output signals by detecting the changing point of address input signals and latching the output signals of a group of memory cells by clock pulse prepared in a semiconductor memory element. CONSTITUTION:Address signal change detection pulse is prepared at every time address input signals change by an address transition detector 2 that detects the changing point of address input signals A0-A7. A memory cell A and a memory cell B are constituted to be able to read alternately. Different data are written beforehand in a semiconductor memory element at the time of writing operation. Thus, an element in which a group of circuits fixed by clock pulse generated by a control circuit is incorporated independently of individual characteristic of memory cell group of the semiconductor element can be obtained.

10. 发明专利

JPS59215099A Check method of semiconductor memory 失效
标题翻译：检查半导体存储器的方法
公开(公告)号：JPS59215099A
公开(公告)日：1984-12-04
申请号：JP8741683
申请日：1983-05-20
申请人： Hitachi Ltd
发明人： YAMADA NOBUO
IPC分类号： G11C29/00 , G01R31/28 , G11C29/50 , G11C29/56
CPC分类号： G11C29/50012 , G11C29/50
摘要： PURPOSE:To attain the confirmation of memory operation to a timing phase difference of an address input signal to a memory element by utilizing a variation in a propagation delay time between gates of semiconductor elements and between delay elements so as to produce a random phase difference automatically. CONSTITUTION:Memory element address input signals Y0,Y1,Yn are inputted during a period T1 while a selector selecting signal SEL is at an H level and X0,X1,Xn are inputted during a period T2 while at a L level. The combination of timing phase differences to address input signals among A0,A1,-An caused while the T1 is changed is changed and the number of combinations is increased as the period is made longer. A chip enable CE and a write/read signal W/R to the semiconductor memory element are inputted with timing waveform, and a signal causing the phase difference to an address input signal group is inputted during the period T1, the memory element is operated normally at the T2 so as to check the effect of the timing phase difference applied during the period T1. In keeping the relation among the T1 and t0,t1-tn pulse width normal, it is possible to obtain various and diversified timing phase differences for the phase difference of the A0, A1, An.
摘要翻译：目的：通过利用半导体元件的栅极之间的延迟元件之间的传播延迟时间的变化和延迟元件之间的变化来获得对地址输入信号到存储元件的定时相位差的存储器操作的确认，以便自动产生随机相位差。构成：在选择器选择信号SEL为H电平的期间T1输入存储元件地址输入信号Y0，Y1，Yn，在时间T2期间输入X0，X1，Xn，同时处于L电平。在T1变化时引起的定时相位差与A0，A1，-An之间的输入信号的组合发生变化，并且随着时间延长，组合数量增加。输入芯片使能CE和对半导体存储元件的写/读信号W / R被输入定时波形，并且在周期T1期间输入引起与地址输入信号组的相位差的信号，存储元件正常工作以检查在T1期间施加的定时相位差的影响。为了保持T1和t0之间的关系，t1-tn脉冲宽度正常，可以获得A0，A1，An的相位差的各种多样化的定时相位差。

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