专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2001143408A RECORDING AND REPRODUCING DEVICE AND DATA ERROR CORRECTING METHOD 失效
公开(公告)号：JP2001143408A
公开(公告)日：2001-05-25
申请号：JP32570099
申请日：1999-11-16
申请人： HITACHI LTD
发明人： ISONO SOICHI , OGAWA HITOSHI , TSUKADA MINORU
IPC分类号： G06F11/10 , G11B20/18 , H03M13/01
摘要： PROBLEM TO BE SOLVED: To provide a magnetic disk drive and a data error correcting method, which shorten the data buffer occupation time for error correction when an SDRAM is used as a data buffer and enables high-speed error corrections and fast data transfer. SOLUTION: An element which enables quick access to data in a page like an SDRAM is used as the data buffer and a means which puts access to the data buffer for error correction together by page units is provided, and error data are rewritten by pages.

2. 发明专利

JP2000349652A STORAGE DEVICE PROVIDED WITH ERROR CORRECTION MEANS 失效
公开(公告)号：JP2000349652A
公开(公告)日：2000-12-15
申请号：JP15961399
申请日：1999-06-07
申请人： HITACHI LTD
发明人： TSUKADA MINORU , NAKAMURA KAZUO , KARASHIMA TETSUJI , KOTANI HIROAKI , NOZOE ATSUSHI , NISHITANI TAKUJI
IPC分类号： G11B20/18 , H03M13/00 , H03M13/29
摘要： PROBLEM TO BE SOLVED: To obtain a storage device where sufficient data reliability is obtained and that flexibly copes with a change in the data reliability of a storage element of a memory chip. SOLUTION: In a flush memory card 501 provided with a memory chip 102 and an interface LSI 106, the memory chip 102 is provided with an internal ECC circuit 104 and the interface LSI 106 is provided with an external ECC circuit 1061. In the case of conducting coding by a product code, first the external ECC circuit 1061 conducts external coding, and then the internal ECC circuit 104 conducts inner coding. Moreover, in the case of reading data, the internal ECC circuit 104 conducts decoding of the internal code and outputs reliability information of line data to the outside of the memory chip 102. In the case of decoding the external code, the external ECC circuit 1061 uses the reliability information of the line data for decoding.

3. 发明专利

JPS5319755A INSPECTING METHOD FOR ELECTRON TUBE CATHODE SURFACE 失效
公开(公告)号：JPS5319755A
公开(公告)日：1978-02-23
申请号：JP9401276
申请日：1976-08-09
申请人： HITACHI LTD
发明人： KAWAGOE HIROMI , TSUKADA MINORU , KOSEKIZAWA KAZUO
IPC分类号： H01J9/42 , G01N21/91 , H01J9/04
摘要： PURPOSE:The alkaline earth metals ternary oxide surface on an electron tube cathode surface and the intermediate layer product formed by reaction of this oxide and a substance metal are melted and removed successively, thereby inspecting the surface.

4. 发明专利

JP2001345712A ENCODING CIRCUIT 失效
公开(公告)号：JP2001345712A
公开(公告)日：2001-12-14
申请号：JP2000166515
申请日：2000-05-31
申请人： HITACHI LTD
发明人： TSUKADA MINORU , ISONO SOICHI
IPC分类号： G11B20/18 , H03M13/01 , H03M13/15
摘要： PROBLEM TO BE SOLVED: To restrict an increase in a circuit scale when an encoding circuit is mounted to hardware in response to a plurality of encoding formats by a magnetic disk drive, etc. SOLUTION: Reference numerals 101a, 101b comprise: a 10-stage shift register 102; an XOR calculator 108; selectors 106, 107; and feedback circuits 103a, 103b. Each coefficient circuit of the feedback circuits 103a, 103b increases coefficient- fold 8-bit user data to be input from an 8-bit bus 104. On the basis of a formation polynomial equation corresponding to a plurality of different encoding codes of each size to be obtained from a common primitive polynomial equation, hardware of a coefficient circuit is shared in coefficients that values of the coefficients are the same or have a small difference.

5. 发明专利

JP2001144628A DATA TRANSFER DEVICE 失效
公开(公告)号：JP2001144628A
公开(公告)日：2001-05-25
申请号：JP32565399
申请日：1999-11-16
申请人： HITACHI LTD
发明人： TSUKADA MINORU , SATAKE KAZUHIKO , OGAWA HITOSHI , ISONO SOICHI
IPC分类号： G06F11/10 , G06F3/06 , G11B20/10 , G11B20/18 , H03M13/27
摘要： PROBLEM TO BE SOLVED: To provide a data transfer device that can transfer user data at a high-speed while efficiently using the capability of a data buffer and correcting the user data on the fly. SOLUTION: A drive control section 820 transfers the user data and an error position and error value information calculated by a CRC circuit 835 to the data buffer 816 in the case that an ECC circuit 830 detects an error in the received user data. A buffer control section 818 stores the data error position and the error value information of the data to an XOR register 8161 when transferring the user data to a host and transfers the data while correcting the data error depending on the error position. A bus width of the buffer 816 is selected to be a multiple of an interleave stage number of the user data. Since the buffer 816 can read all the interleaved data in one clock cycle, a data rearrangement circuit or the like to store the data to the buffer is not required and a bit number for the error position information of the user data can be decreased.

6. 发明专利

JPH11272568A Storage reproducer, error correction method, portable information terminal and digital camera using the same 审中-公开
标题翻译：存储重复器，错误校正方法，便携式信息终端和数字摄像机
公开(公告)号：JPH11272568A
公开(公告)日：1999-10-08
申请号：JP112199
申请日：1999-01-06
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TSUKADA MINORU , NAKAMURA KAZUO , KOTANI HIROAKI , NOZOE ATSUSHI , KARASHIMA TETSUJI , NISHITANI TAKUJI , KATAYAMA YUKARI
IPC分类号： G06F11/10 , G06F12/16
摘要： PROBLEM TO BE SOLVED: To attain a low bit error rate of a file system and reduction of a data reading time while suppressing a circuit scale of an internal ECC circuit in a memory chip. SOLUTION: In writing information into a memory, a memory internal ECC circuit RS encodes information data inputted from an I/O buffer 601 by using a 12 bit delay flip-flop(DFF) 701 (701a, 701b and 701c) and a multiplier 708, and outputs them to an S/A & latch 605. In reading the information from the memory, error information is obtained from the RS encoded data which are read to the S/A &latch 605 from the memory by using the 12 bit DFF 701 and the multiplier 708 and, at the same time, error detection/error correction processing is performed by using a divider 709, a detector 702 (702a and 702b), an NOR circuit 703 and a fourth switch 707, the data are decoded and outputted to the I/O buffer 601.
摘要翻译：要解决的问题：为了在抑制存储芯片内部ECC电路的电路规模的同时，获得文件系统的低位错误率和减少数据读取时间。解决方案：在将信息写入存储器时，存储器内部ECC电路RS通过使用12位延迟触发器（DFF）701（701a，701b和701c）和乘法器708对从I / O缓冲器601输入的信息数据进行编码，并将其输出到S / A和锁存器605.在从存储器读取信息时，通过使用12位DFF 701从存储器读取的S / A和锁存器605从RS编码数据获得错误信息和乘法器708，并且同时通过使用除法器709，检测器702（702a和702b），或非电路703和第四开关707来执行错误检测/纠错处理，对数据进行解码和输出到I / O缓冲器601。

7. 发明专利

JPH11136139A DECODING METHOD AND DEVICE THEREFOR, STORAGE DEVICE, INFORMATION DEVICE USING IT, MEMORY CHIP, RECORD CODE AND OPTICAL COMMUNICATION SYSTEM 失效
公开(公告)号：JPH11136139A
公开(公告)日：1999-05-21
申请号：JP30174597
申请日：1997-11-04
申请人： HITACHI LTD
发明人： KATAYAMA YUKARI , TSUKADA MINORU , NAKAMURA KAZUO , NOZOE ATSUSHI , KARASHIMA TETSUJI
IPC分类号： G11C16/02 , G11C29/00 , G11C29/42 , H03M13/23 , H04L1/00 , H03M13/12
摘要： PROBLEM TO BE SOLVED: To improve a correction capability to a communication path that has an error characteristic of one directivity or a storage medium by performing weighting that is preliminarily defined in accordance of positive or negative of value of difference between a receiving signal and an ideal value at the time of calculating a square error. SOLUTION: When a receiving signal '2' is inputted to a terminal 1101, metric values 4, 5, 0, 9, 11, 6 and 11 are outputted to terminals A to H of a selector 1138. Because an input signal is 2, a Max value is outputted to terminals I, L, M and P of the selector 1138. D terminals of comparators 1139 and 1141 are 1 and D terminals of comparators 1140 and 1142 are 0. Then, path memory 1147 of a state 0 is shifted to the left and 0 is written in a bit at a right edge, the value of the memory 1147 of the state 0 is loaded to path memory 11148 of a state 1 and is shifted to the left and 0 is written at a bit at a right edge. In this way, path memory 1147 to 1150 of each state store user data which correspond to survival paths that reach each state.

8. 发明专利

JPH11143787A RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH11143787A
公开(公告)日：1999-05-28
申请号：JP30406497
申请日：1997-11-06
申请人： HITACHI LTD
发明人： TSUKADA MINORU , NAKAMURA KAZUO , INOUE KIYOSHI , KOTANI HIROAKI , NOZOE ATSUSHI , SHIODA SHIGEMASA , KATAYAMA YUKARI
IPC分类号： G06F12/16 , G06F11/10
摘要： PROBLEM TO BE SOLVED: To achieve the low error-correction-incapability of a file system without increasing the scale of an encoding/decoding circuit in a memory chip. SOLUTION: An outside encoding/decoding circuit 105 outside a memory chip 102 generates an outside coded matrix by encoding each column of an information data matrix, and adding a redundant bit to each column. On the other hand, an inside encoding/decoding circuit 104 inside the memory chip 102 generates a product coded matrix by encoding the line direction of the outside coded matrix, and adding the redundant bit to each line, and stores it in a memory 103. When the memory chip 104 is used as a single body, the inside encoding/decoding circuit 104 generates the inside coded matrix by encoding the line direction of the information data matrix, and adding the redundant bit to each line, and stores it in the memory 103.

9. 发明专利

JPS581498B2 失效
公开(公告)号：JPS581498B2
公开(公告)日：1983-01-11
申请号：JP9401276
申请日：1976-08-09
申请人： HITACHI LTD
发明人： KAWAGOE HIROMI , TSUKADA MINORU , KOSEKIZAWA KAZUO
IPC分类号： H01J9/42 , G01N21/91 , H01J9/04

10. 发明专利

JP2002009631A INVERSE ELEMENT CALCULATION UNIT AND DIVIDER ON FINITE FIELD 失效
公开(公告)号：JP2002009631A
公开(公告)日：2002-01-11
申请号：JP2000194898
申请日：2000-06-23
申请人： HITACHI LTD
发明人： TAIRA SHIGEKI , NISHITANI TAKUJI , OGAWA HITOSHI , TSUKADA MINORU
IPC分类号： G06F11/10 , H03M13/01
摘要： PROBLEM TO BE SOLVED: To provide an inverse element calculation unit and a divider on a finite field that apply inverse element calculation and division onto a finite field GF(2-m), using small amount of calculation by means of a small scale at a high-speed. SOLUTION: The inverse element calculation unit introduces a matrix, denoting a multiplication algorithm derived from a multiplication expression on the basis of components of vectors of operands and calculates a sum of elements of its inverse matrix as the component of vectors of inverse elements. In the inverse element calculation, components of vectors of the inverse elements are separately calculated by the calculation method of the inverse element vector components. In the case of division, an inverse element with respect to a divider is calculated by the calculation method of the inverse element, the inverse element of the divider obtained, thereby is multiplied with a dividend as the calculation of the division.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式