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1. 发明专利

JPH04364553A DISK CONTROLLER 失效
公开(公告)号：JPH04364553A
公开(公告)日：1992-12-16
申请号：JP13903391
申请日：1991-06-11
申请人： HITACHI LTD
发明人： MOCHIDA HIROYUKI , KINOSHITA NOBORU
IPC分类号： G06F11/14 , G06F13/00 , G06F13/10
摘要： PURPOSE:To avoid the continuous occurrence of a data overrun and to improve the reliability of data transfer at low cost by reducing the data transfer speed right after the data overrun is generated. CONSTITUTION:The disk controller 3 detects the retrial of a program by a data overrun retrial detection part 8 when the program is retried right after the data overrun is generated. In response to the detecting operation, a data transfer speed control part 9 decreases the rotating speed of the disk of a disk device 4. Consequently, the speed of data transfer from the disk device 4 to the disk controller 3 is slower than usual in the retrial of the program right after the data overrun occurrence. Consequently, the data transfer in the program retrial after the data overrun occurrence can be performed with high reliability. Thus, the successive occurrence of the data overrun is avoided and the frequency of the data overrun occurrence is suppressed.

2. 发明专利

JPS60222951A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPS60222951A
公开(公告)日：1985-11-07
申请号：JP7842784
申请日：1984-04-20
申请人： HITACHI LTD
发明人： TSUCHIYA CHIHIRO , HORI KAZUYA , KINOSHITA NOBORU , NAKAMURA MASAYUKI
IPC分类号： G06F13/28 , G06F13/38 , H04L29/08
摘要： PURPOSE:To change easily the data transfer speed of an input/output controller by transferring a request demand from a request demand generating means to a processor in accordance with the counted result of a counting means to perform direct memory access (DMA). CONSTITUTION:Information which designates a transfer speed is set to a register 6 through a programmable IO bus 4 by an instruction from a processor 1. At a DMA transfer time, this information is transferred to a count register 7, and counting is performed synchronously with clocks from a clock generating circuit 8, and contents of the register 7 are sent to a NAND gate 9. Meanwhile a request demand from a request generating circuit 10 is given to the gate 9. The request demand is transferred to the processor 1 through a signal line 12 synchronously with the counted result of the register 7 in accordance with speed information set to the register 6. Data received from the processor 1 through a DMA5 is stored temporarily in a buffer 11 and is sent to an input/output device 3.

3. 发明专利

JPH05128050A METHOD FOR DATA RETRIEVAL CONTROL IN ELECTRONIC COMPUTER SYSTEM 失效
公开(公告)号：JPH05128050A
公开(公告)日：1993-05-25
申请号：JP28763791
申请日：1991-11-01
申请人： HITACHI LTD
发明人： KINOSHITA NOBORU , MUNAKATA SHOSHICHI
IPC分类号： G06F3/06 , G06F12/02 , G06F13/10 , G06F13/28
摘要： PURPOSE:To prevent a system from being reduced in its performance by using retrieval information stored in a main storage device and retrieving objective data by using a DMA transfer function and a data retrieving function provided in a disk controller. CONSTITUTION:A microprocessor 301 in the disk control device 3 receives a retrieval command from a processor 1 through a system bus A. In this case, the processor 301 reads out a retrieving character string from a main memory 2 by DMA transfer and stores the read contents in a buffer memory 304. Then the processor 301 reads out file management information stored in a resident table 201 from its leading address to a data transfer buffer 303 by means of DMA transfer. A data retrieving circuit 305 compares the read information with the retrieving character string stored in the memory 304. After ending the retrieval, the processor 301 generates a retrieval result based upon the end state stored in the circuit 305, writes the retrieval result in the end parameter area of a control parameter stored in the main memory 2 by the DMA, and reports the end.

4. 发明专利

JPS61193864A CONTROLLING SYSTEM FOR DOT PRINTER 失效
公开(公告)号：JPS61193864A
公开(公告)日：1986-08-28
申请号：JP3486285
申请日：1985-02-23
申请人： HITACHI LTD
发明人： KINOSHITA NOBORU
IPC分类号： G06F3/12 , B41J2/44 , G06K15/10
摘要： PURPOSE:To process printing data and controlling codes on the same basis, by a system wherein an output from a function memory for storing discrimination information corresponding to printing data and controlling codes developed in a data buffer by an output from a demarcating means is used as a function signal at the time of transfer. CONSTITUTION:The system comprises a system buffer 302 for momentarily storing received data, a data buffer 312 for storing font data and controlling codes in mixture, an address register 304 for converting printing data into font data, a font memory 305, shift registers 306, 307, a shift-controlling circuit 320, a selector 310 for selectively passing either the font data or the controlling codes under selective control by a flip-flop 308, an address register 311 for storing addresses under control by a buffer-controlling circuit 315, a line counter 319, an output buffer 316 for simultaneously transmitting the font data and the controlling codes, and the like.

5. 发明专利

JPS58214927A Device cross call device 失效
标题翻译：设备交叉呼叫设备
公开(公告)号：JPS58214927A
公开(公告)日：1983-12-14
申请号：JP9765982
申请日：1982-06-09
申请人： Hitachi Ltd
发明人： NAKAMURA MASAYUKI , HORI KAZUYA , KINOSHITA NOBORU
IPC分类号： G06F13/14 , G06F9/46
CPC分类号： G06F9/52
摘要： PURPOSE:To simplify the constitution of a titled device, by providing a memory within a device cross call device set between >=2 controllers and a device and opposite to the controller and then sending back a reserving or busy signal. CONSTITUTION:A device cross call device 3 is set between two controllers 1 and 2 which control a device 4. One of these two controllers, e.g., the controller 1 monopolizes the device 4. Therefore, if a reserving signal 5 is delivered, a reserving signal 6 gives a reply to the controller 1 with conditions 7 under which the device is not monopolized by the controller 2. At the same time, an FF13 is set to store that the device is monopolized by the controller 1. An AND circuit 20 is closed to set an output 11 to be delivered to the controller 2 at L. In this case, if the controller 2 supplies a reserving signal 8, a busy signal 9 is delivered in reply from an NAND gate 17. When the monopoly of the controller 1 is over, the FF13 is reset by a release signal 12. Then an access is possible for the controller 2.
摘要翻译：目的：为了简化标题设备的结构，通过在> = 2控制器与设备之间设置的设备交叉呼叫设备内提供存储器，并与控制器相反，然后发回预留或忙信号。构成：设备交叉呼叫装置3设置在控制装置4的两个控制器1和2之间。这两个控制器之一，例如控制器1垄断装置4.因此，如果保留信号5被传送，信号6给出控制器1的答复，其中条件7该设备不被控制器2垄断。同时，FF13被设置为存储设备被控制器1垄断。AND电路20是闭合以将输出11设置为以L传送到控制器2.在这种情况下，如果控制器2提供保留信号8，则从NAND门17应答地传送忙信号9。当控制器的垄断 1结束，FF13由释放信号12复位。然后，控制器2可以进行访问。

6. 发明专利

JPS58213324A Data transfer controlling system 失效
标题翻译：数据传输控制系统
公开(公告)号：JPS58213324A
公开(公告)日：1983-12-12
申请号：JP9484582
申请日：1982-06-04
申请人： Hitachi Ltd
发明人： KINOSHITA NOBORU
IPC分类号： G06F13/12 , G06F13/28
CPC分类号： G06F13/28
摘要： PURPOSE:To save the amount of hardware and to simplify a titled controlling circuit, by bringing the data transfer to the end when data added with a final data display is detected, in an input/output channel device for data prefetch control. CONSTITUTION:In starting data tranfer, data in an input buffer 10 is continued to be written in memories 5 and 6. When the data added with the final data display is read out from the memories 5, 6, it is set to an output data latch 12 and a data transfer end detecting latch 13 and the data transfer from a main storage device to an input/output controller is finished by transferring the data becoming the data transfer end signal to the input/output controller. Thus, the number of data transfers between the main storage device and the input/ output controller is controllable by the same counter.
摘要翻译：目的：为了节省数量的硬件和简化标题控制电路，通过在检测到添加有最终数据显示的数据时将数据传输结束，在数据预取控制的输入/输出通道设备中。构成：在开始数据传输时，输入缓冲器10中的数据继续写入存储器5和6.当从存储器5,6读出添加有最终数据显示的数据时，将其设置为输出数据通过将成为数据传送结束信号的数据传送到输入/输出控制器来完成锁存器12和数据传送结束检测锁存器13以及从主存储装置到输入/输出控制器的数据传送。因此，主存储装置和输入/输出控制器之间的数据传输的数量可由相同的计数器控制。

7. 发明专利

JPS5764833A Input and output extending device 失效
标题翻译：输入和输出扩展器件
公开(公告)号：JPS5764833A
公开(公告)日：1982-04-20
申请号：JP14002780
申请日：1980-10-07
申请人： Hitachi Ltd
发明人： WATANABE YASUMASA , KINOSHITA NOBORU
IPC分类号： G06F9/46 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4022
摘要： PURPOSE:To realize an economical system constitution in accordance with the number of input/output controllers, by securing a mixed connection of an input/output controller and an input/output extending device to a processor. CONSTITUTION:For instance an input/output controller IOC12 among IOCs 12, 14 and 15 is connected directly to a processor 11 by an interface signal line group 6. While the IOCs 14 and 15 are connected to interface signal line groups 7 and 7' via an interface signal line group 6' and input/output extending device EXT13 respectively. The groups 6 and 6' are logically identical with the groups 7 and 7' with the interchangeability to each other. Thus an extending IOC15 is excluded to also eliminate the EXT13. Furthermore the IOC12 can be connected to the EXT13. In such a way, an economical system constitution is realize in accordance with the number of input/output controllers.
摘要翻译：目的：通过将输入/输出控制器和输入/输出扩展设备的混合连接保护到处理器，实现根据输入/输出控制器数量的经济系统结构。构成：例如，IOC12,14和15中的输入/输出控制器IOC12通过接口信号线组6直接连接到处理器11.虽然IOC 14和15经由接口信号线组7和7'连接到接口信号线组7和7' 接口信号线组6'和输入/输出扩展装置EXT13。组6和6'在逻辑上与具有彼此互换性的组7和7'相同。因此，排除扩展的IOC15也可以消除EXT13。此外，IOC12可以连接到EXT13。以这种方式，根据输入/输出控制器的数量来实现经济的系统结构。

8. 发明专利

JPH11203239A SCSI CONTROLLER 失效
公开(公告)号：JPH11203239A
公开(公告)日：1999-07-30
申请号：JP504798
申请日：1998-01-13
申请人： HITACHI LTD
发明人： FUKAYA YASUKATSU , KINOSHITA NOBORU , NARUSE YUKINORI
IPC分类号： G06F13/38 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To attain improvement of working rate in a SCSI connected system for SCSI connecting plural targets to an initiator. SOLUTION: In a SCSI connection system for connecting plural target devices 320 to 32n and a host initiator 31 by way of a SCSI bus 33, a transfer rate is automatically set in mediating with regard to the transfer between the initiator 31, the target 320 and so on at the time of activation and a user is notified of this set transfer rate. Also, when some fault occurs during operation of a main system, a transfer rate control part 312 has the target concerned change the transfer speed and tries continuation of the transfer. Moreover, when a phenomenon is not improved even if the transfer rate changed, it is finally judged to be a fatal fault and the user is notified of stop of the transfer and this state of fault.

9. 发明专利

JPH0962460A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPH0962460A
公开(公告)日：1997-03-07
申请号：JP21436595
申请日：1995-08-23
申请人： HITACHI LTD
发明人： FUKAYA YASUKATSU , KINOSHITA NOBORU
IPC分类号： G06F3/06
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a disk array device by restructuring a RAID by using normal disk devices except a disk where a fault has occurred and putting saved information back to the disk array device after the restructuring. SOLUTION: When an abnormality detection flag 33 and a disk replacement flag 37 become effective, a scheduler 11 alters RAID constitution in intervals of operation. Namely, a control part 32 performs a process for backing up the information on the disk array device 3 to an external storage device 4 and makes a saving end flag 34 effective at the end of the saving operation. At this time, the data are compressed so that the amount of the information is less than the storage capacity of the device 3 after the alteration into (n-1)- disk RAID constitution. Then the control part 32 detects a data compressible flag 35 becoming valid, changes the RAID constitution from (n) disk devices to (n-1) disk devices, and puts the information saved on the external storage device 4 back to the disk array device 3 once the alteration of the RAID is completed.

10. 发明专利

JPH0612190A MAGNETIC DISK CONTROL SYSTEM 失效
公开(公告)号：JPH0612190A
公开(公告)日：1994-01-21
申请号：JP16726192
申请日：1992-06-25
申请人： HITACHI LTD
发明人： MOCHIDA HIROYUKI , KINOSHITA NOBORU
IPC分类号： G06F3/06 , G11B19/02
摘要： PURPOSE:To prevent the increase of an access time in accordance with the multiplex of a disk by simultaneously issuing a command to plural disk devices. CONSTITUTION:A write command is simultaneously issued through disk interface control parts 301a and 301b to disk devices 4a and 4c which spindle-synchronized by a spindle synchronizing signal (d). At the time of detecting that a data trasfer request signal from the disk interface control parts 301 and 301b is arranged by a trasfer request synchronizing circuit 302, a data trasfer control circuit 307 simulatneously outputs a response control signal corresponding to data and a trasfer request to the disk interface control parts 301a and 301b by a data selecting circuit 304 and a control signal selecting circuit 303. Thus, the data can be simulatneously written in the plural disk devices.

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