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    • 4. 发明专利
    • DATA TRANSFER METHOD
    • JPH10154116A
    • 1998-06-09
    • JP31380596
    • 1996-11-25
    • HITACHI LTD
    • YAMAZAKI YASUOMORI TOSHIAKIUKAI TOSHIYUKISHIMIZU MASAAKIKAGIMASA TOYOHIKO
    • G06F13/00
    • PROBLEM TO BE SOLVED: To transfer transmitting data without buffering by an operating system (OS). SOLUTION: In a computer 100 at a sending end, an OS 105 communicates with an OS 205 and collectively confirms whether transmission destination user programs 203 of plural transmitting data which are designated by plural user programs 103 are separately in a receivable state. When a user program 204 at a receiving end does not issue a receiving request, the OS 105 regards the program as unreceivable, collects the transmission of plural transmitting data which are decided as transmittable and instructs a communication device 112. In the device 112, a DMA circuit 113 directly and continuously reads the transmitting data from the buffer 104 of each user program 103, and a communication circuit 114 separately transmits the transmitting data via a channel 300. In a computer 200 at the receiving end, a DMA circuit 213 directly and continuously writes each transmitting data on the buffer 204 of a user program 203 of a transmission destination.
    • 7. 发明专利
    • METHOD AND DEVICE FOR ASSIGNING PROCESSOR
    • JPS6389962A
    • 1988-04-20
    • JP23457886
    • 1986-10-03
    • HITACHI LTD
    • MATSUDA YOSHIKIKAGIMASA TOYOHIKOTAKAHASHI KIKUOYOSHIZUMI SEIICHI
    • G06F15/16G06F15/177
    • PURPOSE:To perform the procedure call of a processor on the other side at high speed, and to contrive to improve the availability of the processor, by switching the call system of the processor according to the state of the processor, in an asymmetric multiprocessor. CONSTITUTION:When the multiprocessor executes the instruction of a main routine in a main memory device 1 by a main processor A100 in a separation mode, and if another processor procedure is called by an instruction call, a signal line 154 from an instruction control circuit 103 goes to '1'. The value of a mode register 3 is '1' because a mode is the separation mode, and a signal line 150 goes to '1'. Therefore, the output 155 of an AND gate 104 goes to '1', and an interruption generation circuit 106 is started up, and an interruption signal 157 goes to '1', then, interruption is generated. As a result, control is delivered to an operating system in the main memory 1, and a process state table is rewritten, and a process assigning request is performed. And processor assignment on a subroutine that is the another processor procedure, is performed.
    • 8. 发明专利
    • Address converter
    • 地址转换器
    • JPS6162952A
    • 1986-03-31
    • JP18463084
    • 1984-09-05
    • Hitachi Ltd
    • IIZUKA TAKAYOSHIGOTO SHIZUOKAGIMASA TOYOHIKOTORII SHUNICHI
    • G06F12/10G06F12/08
    • PURPOSE: To eliminate the unnecessary processing of a super-giant matrix and to process the super-giant matrix directly b dividing an address into a bit showing an address converting mode for matrix ad a matrix into the number, line and column for discriminating the matrix.
      CONSTITUTION: A bit line 1 showing an address is composed of a mode bit 2, matrix number MXN, line number RX and column number CX. The contents of a register MTQ, which is the value of the head address of the matrix table MT is added with the matrix number MXN, and an item 3 in the matrix table MT is formed. The output of a selector is sifted by the bit number, corresponding to the value showing the length of the matrix component, and a displacement 16 in the pages is supplied to an adder 17. The output 16 of a sifter is added by a field 14 from a page table PT by the adder 17 to generate a real address 18.
      COPYRIGHT: (C)1986,JPO&Japio
    • 目的:消除超巨型矩阵的不必要处理,并直接处理超巨型矩阵b将地址划分成一个位,将矩阵矩阵的地址转换模式转换成用于区分矩阵的数字,行和列 。 构成:表示地址的位线1由模式位2,矩阵号MXN,行号RX和列号CX组成。 作为矩阵表MT的头地址的值的寄存器MTQ的内容与矩阵号MXN相加,并且形成矩阵表MT中的项目3。 选择器的输出被对应于表示矩阵分量的长度的值的位数筛选,并且页面中的位移16被提供给加法器17.筛选器的输出端16由字段14 通过加法器17从页表PT生成实地址18。
    • 10. 发明专利
    • REMOTE FILE INPUTTING AND OUTPUTTING METHOD
    • JPH10326217A
    • 1998-12-08
    • JP13643497
    • 1997-05-27
    • HITACHI LTD
    • WATANABE AKISHIMIZU MASAAKIKAGIMASA TOYOHIKO
    • G06F13/12G06F12/00G06F13/00
    • PROBLEM TO BE SOLVED: To obtain an efficient inputting and outputting method by finding a transfer unit according to the size of data requested to be inputted and outputted, adjusting the transfer unit according to the success rate of data transfer, and also adjusting the constitution of transmit and receive date storage areas according to the distribution of transfer units of remote file input/output requests. SOLUTION: Each time a request to input or output a remote file is made, a transfer unit is determined according to the size of the data requested to be inputted or outputted and adjusted according to the success rate of data transfer, and the constitution of transmit and receive data storage areas is adjusted according to the distribution of remote file input/output requests that a client computer is processing. In this system, a transmit data storage area 131 and a receive data storage area 132 are controlled on a client 100 according to a transmit and receive data storage area control table 180. On a server 200, on the other hand, a transmit data storage area 231 and a receive data storage area 232 are controlled with a transmit and receive data storage area control table 280.