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1. 发明专利

JP2000076132A Information processor provided with cache memory 审中-公开
标题翻译：信息处理程序提供缓存记忆
公开(公告)号：JP2000076132A
公开(公告)日：2000-03-14
申请号：JP24527798
申请日：1998-08-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUJINO YASUHIRO , MAEDA SHUJI , FUJIWARA JUNICHI , MAKITA HIROSHI
IPC分类号： G06F12/12 , H04L12/24 , H04L12/26 , H04Q3/545
摘要： PROBLEM TO BE SOLVED: To surely hold data to be cyclically used in a cache memory and to accelerate cache memory use in the information processor of the specified program of a high using frequency.
SOLUTION: This information processor is provided with a means 134 for indicating that it is during LRU control out-of-object registration, the means 1314 for indicating the LRU control out-of-object of respective entries 131, the instruction means of LRU control out-of-object registration start to the cache memory 13 by a processor, the means for being under the LRU control out-of-object registration by an instruction and turning the entry to the LRU control out-of-object after the completion of a normal cache operation by an instruction code to be used at the execution of instruction thereafter and the data, the instruction means of LRU control out-of-object registration end to the cache memory by the processor, the cancellation means of a state under the LRU control out-of-object registration by the instruction and the application means of LRU algorithm for closing the entry of the LRU control out-of-object to the entry of another way as the out-of-object of the LRU algorithm.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：确保将数据循环使用在高速缓冲存储器中，并且在高使用频率的指定程序的信息处理器中加速缓存存储器的使用。解决方案：该信息处理器设置有用于指示在LRU控制对象外注册期间的装置134，用于指示各个条目131的对象外的LRU控制的装置1314，LRU控制的指令装置通过处理器将对象外注册开始到高速缓冲存储器13，用于通过指令进行LRU控制进行对象外注册的装置，并且在完成之后将该条目转换为对象外的LRU控制通过在其后执行指令时要使用的指令代码进行正常的高速缓存操作和数据，由处理器将对象登记的指令装置控制到高速缓冲存储器， LRU通过LRU算法的指令和应用程序控制对象外注册，将LRU控制对象外的条目作为LRU算法的对象外的另一种方式进入。

2. 发明专利

JPH0251958A CHECKING SYSTEM FOR COMPETITIVE SERVICE OF COMMUNICATION NETWORK 失效
公开(公告)号：JPH0251958A
公开(公告)日：1990-02-21
申请号：JP20200488
申请日：1988-08-15
申请人： HITACHI LTD
发明人： KOBARI KUNIHIKO , FUJINO YASUHIRO , SHINPO ISAO , TAKEMURA TETSUO
IPC分类号： H04M3/42 , H04Q3/545
摘要： PURPOSE:To attain wide service competitive check by recognizing the additional service generated at different nodes caused by a single call. CONSTITUTION:A service control node is equipped with the service control functions of an exchange node (a) and an exchange node (b). When the additional service is generated at the service control node, a means to allocate a uniquely recognizable network call number(NCR) in a communication network to the said call, a means to store an additional service using condition, and a means to circulate the NCR between the nodes by the call concerned to the exchange node are provided. When the new additional service is generated in the call concerned, the service control node reads the additional service using condition of the call concerned by the notified NCR, and the competitive check is executed by additional service competitive condition defined beforehand for the existing additional service and a newly additional service classification. Thus, whether the newly additional service generated at the different node is accepted or rejected is determined.

3. 发明专利

JPS6457340A METHOD AND SYSTEM FOR PROCESSING DATA FLOW COMPUTER 失效
公开(公告)号：JPS6457340A
公开(公告)日：1989-03-03
申请号：JP21271387
申请日：1987-08-28
申请人： HITACHI LTD
发明人： FUJINO YASUHIRO , YAMAMOTO TOSHIAKI , TAGUCHI HARUKI
IPC分类号： G06F15/82 , G06F9/44
摘要： PURPOSE:To efficiently store, refer and correct data, by adding a function for automatically acquiring a storage area to operation for acquiring a new color. CONSTITUTION:An instruction token 41 arrives at a memory part 21 corresponding to colors by an instruction code 412, a color 411 and an index 413 are extracted by a control part 211 and a real address to be accessed is calculated by an address calculation part 212. The control part 211 accesses a found address memory part 213 and outputs the accesses result to a link memory part 3. Thus, the color always corresponds to the storage area at the rate of 1 to 1 can be guaranteed. Since a new area is acquired and processing for area acquisition is not required, processing speed can be improved.

4. 发明专利

JP2002237845A WIDE AREA MULTICAST COMMUNICATION METHOD 审中-公开
公开(公告)号：JP2002237845A
公开(公告)日：2002-08-23
申请号：JP2001382470
申请日：2001-12-17
申请人： HITACHI LTD
发明人： EBATA TOMOKAZU , ORIMO MASAYUKI , MORITA TOYOHISA , NAKADAI HIROKI , FUJINO YASUHIRO
IPC分类号： H04L12/70 , H04L12/761 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To realize an efficient multicast communication capable of easily coping with the addition and elimination of nodes in a system in a wide area distribution system. SOLUTION: Each node 11 advises the other nodes constituting the system of a message ID to be received by its own node. The node receiving this message correlates the ID with the address of the generation source node, and stores them in a table 1103 of its own node. When transmitting the message, the ID of the message to be sent is discriminated, the address of the node to which the message is sent is discriminated on the basis of the table 1103 in which the ID of the message is correlated with the address of a node receiving the message having this ID, and the message is transmitted.

5. 发明专利

JP2001217874A WIDE AREA MULTI-CAST COMMUNICATION METHOD 失效
公开(公告)号：JP2001217874A
公开(公告)日：2001-08-10
申请号：JP2000391838
申请日：2000-12-20
申请人： HITACHI LTD
发明人： EBATA TOMOKAZU , ORIMO MASAYUKI , MORITA TOYOHISA , NAKADAI HIROKI , FUJINO YASUHIRO
IPC分类号： H04L12/18 , H04L12/28 , H04L12/761 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a wide area multi-cast communication method by which efficient multi-cast communication can be realized by easily coping with addition/deletion of a node in a wide area distribution system. SOLUTION: Each node 11 informs an other node being a component of the wide area distribution system about a message ID to be received its own node. The node receiving this massage stores an ID and a generation source node in cross-reference with each other to a table 1103 of its own node. In the case of transmitting the message, the ID of the message to be sent is discriminated and an address of the node to which the message is to be sent is discriminated and the message is sent to the address on the basis of the table 1103 where the message ID and an address of a node receiving the message with the ID are cross-referenced with each other.

6. 发明专利

JPH0495432A TRAFFIC APPLICATION VALUE GENERATING SYSTEM 失效
公开(公告)号：JPH0495432A
公开(公告)日：1992-03-27
申请号：JP21167590
申请日：1990-08-13
申请人： HITACHI LTD
发明人： IDO NOBUHIKO , FUJINO YASUHIRO
IPC分类号： G06F13/14 , H04L12/28 , H04L25/02 , H04Q3/00
摘要： PURPOSE:To generate a traffic application value as that suitable for traffic control in an ATM communication network by referencing the result of traffic measurement as to each communication having been implemented already before every communication as traffic history information. CONSTITUTION:A position of a traffic history table 34 coincident with arguments such as a call class, a user identifier and a time zone is obtained by indexing and referencing sequentially a call class branch table 31, a terminal user branch table 32 and a time zone branch table 33 based on the call class, the user identifier and the time zone used as arguments in the traffic history data read processing at first. In the traffic application generating processing based on the result of plural sets of traffic measurements, and in the traffic history data revision processing where they are set as the traffic application values in a call setting signal, the traffic application value is generated as a mean value of each of maximum zone, mean zone, and mean burst length and the position of a traffic history table coincident with each item similarly in the case of the traffic history data read processing.

7. 发明专利

JPH0362655A SYSTEM OF EXCHANGE PROVIDING ACCOMMODATION FOR NON-FRAME TRANSMISSION TERMINAL 失效
公开(公告)号：JPH0362655A
公开(公告)日：1991-03-18
申请号：JP19685189
申请日：1989-07-31
申请人： HITACHI LTD
发明人： FUJINO YASUHIRO , SHINPO ISAO
IPC分类号： H04Q3/42 , H04M3/00
摘要： PURPOSE:To design the system such that only the revision of an integrated software is enough for the addition or supply of a new service by accommodating analog or character terminal equipments to one and same exchange together with ISDN terminal equipments. CONSTITUTION:PB/DP telephone sets 3 as plural analog terminal equipments and plural ISDN terminal equipments 4 are accommodated in an exchange main body via an interface device 2 provided in the exchange 1 in this embodiment. The telephone set 3 is accommodated in a channel switch 11 in the device 1 via a telephone set relevant subscriber circuit 21 and also once accommodated in a microprocessor 24 as an interface control circuit via PB/DP receiver 22 relevant to the circuit 21 and accommodated in a main body processor 12 as a controller in the exchange main body. On the other hand, the terminal equipment 4 is accommodated to the channel switch 11 via D-channel processing circuit 23 relevant to the terminal equipment in compliance with the CCITT. I.441, and on the other hand, accommodated once in the processor 24 via the D-channel processing circuit 23 and accommodated in the processor 12.

8. 发明专利

JPH01142832A PROCESSING SYSTEM FOR DATA FLOW COMPUTER 失效
公开(公告)号：JPH01142832A
公开(公告)日：1989-06-05
申请号：JP30021487
申请日：1987-11-30
申请人： HITACHI LTD
发明人： FUJINO YASUHIRO , TAGUCHI HARUKI , YAMAMOTO TOSHIAKI
IPC分类号： G06F15/16 , G06F9/44 , G06F15/82
摘要： PURPOSE:To transmit/receive a token between functions independently of a function call system by providing the title system with a means for storing a code to be used between plural functions in common and a means for using the code as retrieving information to detect firing. CONSTITUTION:In case of sending data necessary for an instruction existing in a function B based on a SEND instruction in a function A, a token having Rec-des in its data field V is extracted from an operand working queue 1 and data (n) in a REC instruction stored in an address des 1 of a program memory 2 are read out and stored in a token queuing memory 3 of a firing detecting part. Then, a token having Send-data accesses data in the SEND instruction stored in an address des 2 and stores the accessed result in the memory 3. The memory 3 is retrieved by using (n) as a retrieval key, the queuing state of the corresponding REC instruction is detected and an instruction code is transferred to an operation part 4. Consequently, a token can be transmitted/ received between plural functions independently of a function call.

9. 发明专利

JPS63271536A TOKEN ERASING METHOD FOR DATA FLOW COMPUTER 失效
公开(公告)号：JPS63271536A
公开(公告)日：1988-11-09
申请号：JP10432187
申请日：1987-04-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FUJINO YASUHIRO , TAGUCHI HARUKI , YAMAMOTO TOSHIAKI , NAGASE HIROSHI
IPC分类号： G06F15/82 , G06F9/44
摘要： PURPOSE:To erase the token of only a specific process without interfering with another process by instructing a certain specific part of a circulation system as to the use inhibition of a color, discarding a token of the color at the time of arrival at the specific part, and erasing all tokens and then registering the color in a free color control stack. CONSTITUTION:The specific part (e.g. link memory part 5) of the circulation system discards all tokens of the color reaching the part. Namely, the novel token of the color does not circulates in the circulation system. Tokens of the color which remain in a matching store part 1 and the queuing memory 41 of a structure memory part 4 are all erased. Consequently, all the tokens of the color in a data flow computer are erased. Further, the emptiness of the color is registered after said processing, and then normal operation is performed in subsequent processes even if the color is used newly.

10. 发明专利

JPS62256043A PRIORITY CONTROL SYSTEM FOR DATA FLOW COMPUTER 失效
公开(公告)号：JPS62256043A
公开(公告)日：1987-11-07
申请号：JP9796886
申请日：1986-04-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FUJINO YASUHIRO , TAGUCHI HARUKI , YAMAMOTO TOSHIAKI , NAGASE HIROSHI
IPC分类号： G06F15/82 , G06F9/44
摘要： PURPOSE:To reduce the response time of a process, and to enable the process to be performed more appropriately, by processing a colored token arriving at random at a processing circuit, from the token having high priority. CONSTITUTION:The titled system is constituted so that a priority control circuit 10 is added on the front stage of a firing detection circuit (MS)4. In the priority control circuit 10, a gate 1 to allocate the colored token to a queue classified by priority, a queue 21 of high-order priority, a queue 22 of low-order priority, and a readout circuit 3 to read out the token from respective queue, are provided between an output circuit 6, and the MS4. The staining token on which the priority is attached, is stacked at a process waiting queue corresponding to the priority in the processing circuit. Also, at respective processing circuit, the token is read out from the queue of high-order priority when the token is registered at the high-order queue, and is read out from the queue of next high-order priority when it is not registered, and is processed, therefore, it is possible to perform a priority control.

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