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1. 发明专利

JPH11330158A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11330158A
公开(公告)日：1999-11-30
申请号：JP13013798
申请日：1998-05-13
申请人： HITACHI LTD
发明人： KIKUCHI HIROSHI , ANDO HIDEKO
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a package which is improved in a connection reliability of contact parts between bump electrodes and substrate electrodes. SOLUTION: A semiconductor chip 2, having solder bumps 3 formed on bonding pads BP, is connected face-down to a major surface of a package substrate 1, an under-fill resin 5 is filled in a gap between the chip 2 and the substrate 1 to lighten stress, and surfaces of the chip 2, the substrate 1 and the bumps 3 are covered with an insulating layer 6 which has better adhesion than the under-fill resin 5. As a result, there can be obtained a package, which can positively protect elements formed in the chip 2 and connection parts between the bumps 2 and upper electrodes 4 from water or pollutants.

2. 发明专利

JPH09275172A SEMICONDUCTOR DEVICE AND MOUNTING STRUCTURE THEREFOR 失效
公开(公告)号：JPH09275172A
公开(公告)日：1997-10-21
申请号：JP10189996
申请日：1996-04-01
申请人： HITACHI LTD
发明人： ANDO HIDEKO , KIKUCHI HIROSHI
IPC分类号： H01L21/60 , H01L23/12 , H01L23/32 , H01L23/467
摘要： PROBLEM TO BE SOLVED: To improve the heat radiation and make the structure thinner. SOLUTION: A BGA IC 10 mounted in a housing 29 having a blower 30 comprises a pellet 11 CCB-connected to one main face of a substrate 17 through connecting terminals 21 formed from bumps, a reinforcing resin layer 25 formed in a small space defined by a group of connecting terminals 12 between the pellet 11 and a substrate 17, and protrusions 16 for generating turbulent flow are formed on the upper face of the pellet 11. When a flow from a blower 30 touches the protrusion 16, a turbulent flow is generated round these protrusions to efficiently absorb the heat generated in the pellet 11, thus efficiently radiating the heat of the pellet 11. The heat radiated by the flow is discharged by the flow to outside of the housing 29.

3. 发明专利

JP2003273273A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2003273273A
公开(公告)日：2003-09-26
申请号：JP2002073159
申请日：2002-03-15
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ANDO HIDEKO , MIYAMOTO SEIJI
IPC分类号： H05K3/46 , H01L23/12 , H01L23/498 , H01L23/66 , H05K1/00 , H05K1/02
CPC分类号： H01L23/66 , H01L23/49822 , H01L2224/16 , H01L2224/16235 , H01L2924/15173 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H05K1/024 , H05K1/0298 , H05K3/4602 , H05K2201/0191
摘要： PROBLEM TO BE SOLVED: To accurately regulate the characteristic impedance of a wiring. SOLUTION: A semiconductor device comprises a first insulating layer 4i between a first wiring layer 4d and a second wiring layer 4e of a core layer 4c having a thickness (D) increased relative to the first wiring 4m of the layer 4e disposed in a through hole 4r of the core layer 4c in a package board 4, a thickness (C) of the layer 4j between the first wiring layer 4d of the reverse side plane layer decreased. Thus, the coupling of a power source plane of the first wiring layer 4d on the surface of the core layer 4c and the impedance of the first wiring 4m and a second wiring 4n is weakened, and a power source plane shown in a reverse side third wiring layer 4f and the impedance of the first wiring 4m or the second wiring 4n can be strengthened, and the unevenness of the characteristic impedance between the wiring 4m directly on the hole 4r and the second wiring 4n disposed by avoiding from directly above the hole 4r can be reduced. COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：准确调节布线的特性阻抗。解决方案：半导体器件包括第一布线层4d和芯层4c的第二布线层4e之间的第一绝缘层4i，芯层4c的厚度（D）相对于布置在层4e中的层4e的第一布线4m增加封装板4中的芯层4c的通孔4r，反面平面层的第一布线层4d之间的层4j的厚度（C）减小。因此，芯层4c的表面上的第一配线层4d的电源面与第一配线4m的阻抗与第二配线4n的耦合被削弱，反之，第三配线可以加强布线层4f和第一布线4m或第二布线4n的阻抗，并且通过从孔4r的正上方避开而直接设置在孔4r上的布线4m和第二布线4n之间的特性阻抗的不均匀性可以减少版权所有（C）2003，JPO

4. 发明专利

JP2000068313A SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE USING THE SAME 失效
公开(公告)号：JP2000068313A
公开(公告)日：2000-03-03
申请号：JP24652398
申请日：1998-08-18
申请人： HITACHI LTD
发明人： ANDO HIDEKO , KIKUCHI HIROSHI , YOSHIDA IKUO , SATO TOSHIHIKO
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To increase effective area of solder bump arrangement. SOLUTION: Electrode contacting openings 17 are opened on a shielding film 16, that coats the main surface of an active region 11 side of a semiconductor chip 10, solder bumps 12 are protruded at positions apart from the electrode contacting openings 17, and the solder bumps 12 are electrically connected to the electrode connecting openings 17 with electrical wiring 18 laid on the surface of the shielding film 16. Height h of the solder bumps 12, distance L between the edge of a solder bump 12 and an electrode connecting opening 17, opening width a of the electrode connecting opening 17, and thickness t of the shielding film are designed so as to satisfy the inequality (h/L)

5. 发明专利

JPH1140608A SEMICONDUCTOR DEVICE AND ITS MOUNTING METHOD 失效
公开(公告)号：JPH1140608A
公开(公告)日：1999-02-12
申请号：JP19699497
申请日：1997-07-23
申请人： HITACHI LTD
发明人： KIKUCHI HIROSHI , ANDO HIDEKO
IPC分类号： H01L21/60 , H05K3/30 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To extend the connection life of a solder bump, and also, improve the connection reliability of the solder bump. SOLUTION: This device comprises a device body part 3 equipped with an element mounting board 2 on which a semiconductor chip 1 is mounted, a printed board 5 where the device body 3 is mounted through a solder bump 4, and a support member 6 which is made of material larger in thermal expansion coefficient than the solder to form the solder bump 4 and further is made lower than the level of the solder bump 4 after mounting of the device body part 3. Then, at fusion of the solder bump 4 at the time of mounting the device body part 3 on the printed board 5 through the solder bump 4, the support member 6 contacts with the element mounting board 2 and the printed board 5, and supports the device body part 3.

6. 发明专利

JPH09213743A ELECTRONIC COMPONENT AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09213743A
公开(公告)日：1997-08-15
申请号：JP1884396
申请日：1996-02-05
申请人： HITACHI LTD
发明人： ANDO HIDEKO , KIKUCHI HIROSHI , SATO TOSHIHIKO , HAYASHIDA TETSUYA
IPC分类号： H01L21/60 , H01L23/12 , H05K3/30 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To make it possible to easily align a semiconductor device with a wiring board and prevent more bumps than specified from being crushed by forming a plurality of support pins each of which consists of a prop section for positioning and a spacer section that maintain a specified gap between the semiconductor device and the wiring board. SOLUTION: This electronic component consists of a semiconductor device 3 formed by mounting a semiconductor chip 2 with circuit elements formed thereon on a package board 5 having bumps 10, and sealing them; a wiring board 4 mounted with the semiconductor device 3; and a plurality of support pins 12. Each of the support pins 12 contains a prop section 12a that is fit, on one side, in a positioning hole 4a formed in the wiring board 4, and thus holds the semiconductor device 3 in a specified position on the wiring board 4. Each support pin also contains a spacer section 12b projected outward that is formed in the middle of the prop section 12a and is placed between the semiconductor device 3 and the wiring board 4 to maintain a specified gap between them during a bump 10 reflow cycle.

7. 发明专利

JP2008034890A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008034890A
公开(公告)日：2008-02-14
申请号：JP2007279064
申请日：2007-10-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIKUCHI HIROSHI , KUBO TAKASHI , SUGA TAKU , SASAKI HIROYASU , ANDO HIDEKO , FUKUHARA MASANORI , ISOMURA SATORU
IPC分类号： H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To attain miniaturization of a semiconductor device. SOLUTION: The semiconductor device is composed of: a package substrate 4 having a microstripline 4g composed of a surface layer wiring 4c for a signal and a GND layer 4f; a high frequency semiconductor chip 2 mounted on the principal surface 4a of the package substrate 4 by means of flip-chip connection; a coaxial cable 7 where a core wire 7a is electrically connected to the surface layer wiring 4c for a signal; an underfill resin 6 for protecting the flip-chip connection portion of the semiconductor chip 2; a plurality of ball electrodes 3 arranged on the rear surface 4b of the package substrate 4; and a coaxial connector 11 provided to a frame member 8 attached to the package substrate 4; and provided with a structure which can transmit a high frequency signal from the coaxial cable 7 to all the surface layers of the package substrate 4 by only the microstripline, thereby miniaturization of the package can be attained by arranging the plurality of ball electrodes 3 in an array on the rear surface 4b of the package substrate 4. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了实现半导体器件的小型化。解决方案：半导体器件由以下组成：具有由用于信号的表面层布线4c和GND层4f构成的微带线4g的封装基板4; 通过倒装芯片连接安装在封装基板4的主表面4a上的高频半导体芯片2; 同轴电缆7，其中芯线7a电连接到用于信号的表层布线4c; 用于保护半导体芯片2的倒装芯片连接部分的底部填充树脂6; 布置在封装基板4的后表面4b上的多个球电极3; 以及设置在安装在封装基板4上的框架部件8的同轴连接器11; 并且具有能够通过仅由微带线从同轴电缆7将高频信号发送到封装基板4的全部表层的结构，由此能够通过将多个球电极3配置在阵列位于封装基板4的背面4b上。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2003258142A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003258142A
公开(公告)日：2003-09-12
申请号：JP2002053222
申请日：2002-02-28
申请人： HITACHI LTD
发明人： KIKUCHI HIROSHI , KUBO TAKASHI , SUGA TAKU , SASAKI HIROYASU , ANDO HIDEKO , FUKUHARA MASANORI , ISOMURA SATORU
IPC分类号： H01L23/12 , H01L23/02 , H01P1/00
摘要： PROBLEM TO BE SOLVED: To miniaturize a semiconductor device. SOLUTION: There are provided a package substrate 4 having a microstrip line 4g, composed of a signal surface layer wiring 4c and a GND layer 4f, a high-frequency semiconductor chip 2 mounted on a principal surface 4a of the package 4 via flip-chip connection, a coaxial cable 7 having a core wire 7a electrically connected to a signal surface layer wiring 4c, and underfilled resin 6 for protecting the flip-chip connection portion of the semiconductor chip 2, a plurality of ball electrodes 3 each being disposed in a back surface 4b of the package substrate 4, and a coaxial connector 11 provided on a frame member 8 mounted on the package substrate 4. A high-frequency signal from the coaxial cable 7 can be transmitted to the entire surface layer of the package substrate 4. The package is miniaturized, by arranging all of the plurality of the ball electrodes 3 in an array configuration, on the back surface 4b of the package substrate 4. COPYRIGHT: (C)2003,JPO

9. 发明专利

JP2002353365A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002353365A
公开(公告)日：2002-12-06
申请号：JP2001161914
申请日：2001-05-30
申请人： HITACHI LTD
发明人： NAGATA TATSUYA , MIYAMOTO SEIJI , ANDO HIDEKO
IPC分类号： H01L23/12 , H01L23/498 , H05K1/02 , H05K1/11 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To reduce the generation of noises by preventing a semiconductor device from being large-sized. SOLUTION: The device is provided with a base 5 where surface layers 9, 11 are provided on both sides of a core layer 7 formed by a circuit board, and a semiconductor device 1 mounted on a base 5. The semiconductor device 1 is bonded with one surface layer 9 by bonding materials 3, and a plurality of external terminals 55 are arranged on the other surface layer 11. In the core layer 7, there are formed a plurality of through holes 41, 43, 45, 75, 77 which electrically connect the plurality of external terminals 55 with the semiconductor device 1. The plurality of through hole 41, 43, 45, 75, 77 comprises the plurality of array through holes 41, 43, 45 arranged in correspondence with array of the plurality of external terminals 55, and one or more than two additional through holes 75, 77 arranged between the plurality of array through holes 41, 43, 45.

10. 发明专利

JPH10242179A MANUFACTURE OF SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JPH10242179A
公开(公告)日：1998-09-11
申请号：JP3874397
申请日：1997-02-24
申请人： HITACHI LTD
发明人： ANDO HIDEKO , KIKUCHI HIROSHI
IPC分类号： H01L21/56
摘要： PROBLEM TO BE SOLVED: To increase the work efficiency on the occasion of injecting resin, by injecting the resin at an ordinary temperature without warming a semiconductor package and the resin, and filling up between the semiconductor chip and a wiring board with resin by primary baking after that. SOLUTION: When a semiconductor package are manufactured by filling up between a semiconductor chip 1 flip-chip-mounted and a wiring board 3 with a resin 7, on the occasion of filling with the resin 7, the resin 7 is injected at a normal temperature without warming semiconductor packages 1-3 and the resin 7. After that, between the semiconductor chip 1 and the wiring board 3 is filled up with the resin 7 by primary baking being preparatory baking for making the resin 7 and the members 1-3 get to fit. For example, the needle 5 of a resin injecting syringe 4 is thrusted into the gap between the LSI ship 1 of an LSI package and the wiring board 3 downwards from the vertical upside, and the resin 7 is injected. Next, they are all put into a baking furnace 10 together with a product case 9 at the time of injection with the bottom surface of the LSI package horizontal, and resin 7 filling and primary baking are performed simultaneously.

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