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1. 发明专利

JPS612969B2 JPS612969B2 - 失效
公开(公告)号：JPS612969B2
公开(公告)日：1986-01-29
申请号：JP9224280
申请日：1980-07-08
申请人： Hitachi Electronics
发明人： ISHII SHIGERU , HIBINO KATSUHIKO , JO AKIO
IPC分类号： G06F7/64 , G06F17/13
CPC分类号： G06F17/13

2. 发明专利

JPS5884346A ARITHMETIC CONTROLLING SYSTEM OF DIGITAL DIFFERENTIAL ANALYZER 失效
公开(公告)号：JPS5884346A
公开(公告)日：1983-05-20
申请号：JP18224881
申请日：1981-11-16
申请人： HITACHI ELECTRONICS
发明人： HIBINO KATSUHIKO
IPC分类号： G06F7/64
摘要： PURPOSE:To eliminate an arithmetic error which is caused when interlocking two digital differential amalizers DDA to each other, by applying the output of the arithmetic control signal obtained through the decoding within one DDA to the other DDA in case the arithmetic control is given to plural DDAs through a digital computer, etc. CONSTITUTION:The arithmetic control selection signal is fed to a data bus 2 from a digital computer 1, and then decoded through the decoding parts 3 and 7 of the two DDAs. Then an indication is given to the selectors 12 and 17 to select whether the own arithmetic control signal or the arithmetic control input signal given from another DDA. Then, the arithmetic control signals 5 and 13 given from the selectors 12 and 17 are fed to the arithmetic parts 4 and 9 of the DDAs. Thus, the parts 4 and 9 are actuated with the arithmetic control signal sent from a decoder 3 or 7.

3. 发明专利

JPS57203138A ASYNCHRONOUS OUTPUT SYSTEM OF DIGITAL DIFFERENTIAL ANALYZER 失效
公开(公告)号：JPS57203138A
公开(公告)日：1982-12-13
申请号：JP8818181
申请日：1981-06-10
申请人： HITACHI ELECTRONICS
发明人： HIBINO KATSUHIKO , HAMAGUCHI YASUHIRO , SOGOU SABUROU
IPC分类号： H03K19/177 , G06F7/64
摘要： PURPOSE:To easily discriminate an error in fetching by adding a one-bit signal to output data of a specific address. CONSTITUTION:An address signal 2 from a digital differential analyzer DDA is decoded by a decoder 5 and if there is an address to be outputted, a gate 3 is opened by a decoding output 4 to store the output data 1 of the DDA in a buffer memory 7. In this case, while the gate 3 is opened for data on a specific address, connection with the memory 7 is made to store the data in the memory 7 together with an added one-bit signal. A CPU8 fetches data from the memory 7 one after another, but the range of data fetched at a time is made clear by finding the specific bit in the data, so that an error in fetching even if occurs is discriminated easily.

4. 发明专利

JPS57114942A OPERATION OUTPUT CIRCUIT FOR DIGITAL DIFFERENTIATING ANALYZER 失效
公开(公告)号：JPS57114942A
公开(公告)日：1982-07-17
申请号：JP147081
申请日：1981-01-08
申请人： HITACHI ELECTRONICS
发明人： JIYOU AKIO , HIBINO KATSUHIKO , ISHII SHIGERU
IPC分类号： G06F7/64
摘要： PURPOSE:To simplify the constitution, by providing a logical circuit which adds the content of an R register and a Y register of a digital differentiation analyzer and transmits a signal representing the increment from a signal indicating the polarity and overflow. CONSTITUTION:A Y register RY adding and storing a plurality of signals representing increments, and an R register RR having almost a half range of the content value changed range of the RY, in which the content is circulated between the maxiumum and minimum value, are provided, and the content of the RR and RY is added at an adder AD and the result of addition R+Y is given to the RR. The adder AD transmits a polarity signal P indicating the changing direction of state of addition and an overflow signal FO generated when the result of addition is plus or minus 1 or more, to a logical circuit LG. The circuit LG transmits the signal P as a polarity bit BP as it is, a logical product G between a signal inverting IN the signal OF and the signal P is taken and stored at a latch circuit LAT according to a latch signal LS as a numeral bit BN, and the signals BP, BN are transmitted to increment memories MZ1-MZ4.

5. 发明专利

JPS5719874A PARALLEL OPERATION SYSTEM IN DIGITAL DIFFERENTIAL ANALYZER 失效
公开(公告)号：JPS5719874A
公开(公告)日：1982-02-02
申请号：JP9224280
申请日：1980-07-08
申请人： HITACHI ELECTRONICS
发明人： ISHII SHIGERU , HIBINO KATSUHIKO , JIYOU AKIO
IPC分类号： G06F7/64 , G06F17/13
摘要： PURPOSE:To perform more effectively a parallel operation in a differential analyzer by performing, in parallel, action of a connection memory and that of the first and second adder action on and after the first and the second multipliers. CONSTITUTION:A plural number of operation input are added mutually on the first adder AD1 and an output from the adder AD1 is held in a latch circuit LAT until next pulses are generated according to timing pulse from an address counter CUA. Inclusions held on this circuit LAT are added to the first multiplier ML1, the second multiplier ML2 and an output circuit OZ by an adder assignment from connection memories MC1-MC4, a scale memory MS, a Y resistor RY and an R register RR and stated operations are done. In parallel to this operation, by assigning the memories MC1-MC3 with a stated address and by performing adding action in a next step for a fixed operation in memories MC1-MC3 and the adder AD1, an operation in a digital differential analyzer is done in parallel.

6. 发明专利

JPS5818749A CONTROLLING SYSTEM OF MULTIVARIABLE FUNCTION GENERATING DEVICE 失效
公开(公告)号：JPS5818749A
公开(公告)日：1983-02-03
申请号：JP11610581
申请日：1981-07-23
申请人： HITACHI ELECTRONICS
发明人： HIBINO KATSUHIKO , KAWAMURA YOSHIHISA , HAMAGUCHI YASUHIRO
IPC分类号： G06F7/64
摘要： PURPOSE:To eliminate any error from the operation results by obtaining correct operation results from the initial value in terms of operations performed under the cooperation of a digital differential analyzer (DDA) and a multivariable function generating device (DDFG). CONSTITUTION:Control signal outputs LS2-LS4 and AND gates G1-G3 of a control memory MP are individually inserted, and, when a switch S is set to the off condition, each variable latching circuit LX, LY, and LZ do not make any holding operations because the control signal outputs LS2-LS4 and the AND gates G1-G3 are also set to the off condition and no gradient value is sent from a gradient value memory MG. Therefore, when a timing pulse generator TPG is operated under the condition where the switch S is set to the off condition before starting the whole arithmetic operation, an interval definition point memory MNB or a interval definition point controlling circuit DC, a variable memory MV, the control memory MP, the variable latching circuit LX, etc., of a multivariable function generating device (DDFG) operate, and a variable outputted from a register YR at a digital differential analyser (DDA) side is held by the variable latching circuit LX. Moreover, an approximate partition point in an interval definition point memory MN coincides with the outputted variable by the operations of the interval definition point memory MNB or the interval definition point controlling circuit DC.

7. 发明专利

JPS55102048A OUTPUT SYSTEM OF DIGITAL DIFFERENTIATION ANALYZER 失效
公开(公告)号：JPS55102048A
公开(公告)日：1980-08-04
申请号：JP886479
申请日：1979-01-29
申请人： HITACHI ELECTRONICS
发明人： HIBINO KATSUHIKO , JIYOU AKIO
IPC分类号： G06F7/64
摘要： PURPOSE:To extend the range of application and to make easy the operation, by forming the negative feedback loop between the input and output of the operation circuit when the operation circuit is operated as the output unit and using the content of Y register as the output. CONSTITUTION:The selector SL5 selecting the output of the polarity inverter IV and the output of the output circuit OZ and delivering the result to the DELTAZ memories MZ1-MZ4 is provided in the output side of the output circuit OZ, and the operation mode instruction signal is made by the output unit mode newly provided. The output unit mode selects the output of the polarity inverter IV to the selector SL5 to store it to the DELTAZ memories MZ1-MZ4 and negative feedback loop is formed between the input and output of the operation circuit OP and the content of the Y register RY is used as the output. Accordingly, since the entire amplitude of the result of operation can easily be picked up as the output, it is possible to give it to each unit of peripheral as it is.

8. 发明专利

JPS57168343A MAXIMUM VALUE DETECTING CIRCUIT 失效
公开(公告)号：JPS57168343A
公开(公告)日：1982-10-16
申请号：JP5314781
申请日：1981-04-10
申请人： HITACHI ELECTRONICS
发明人： HAMAGUCHI YASUHIRO , HIBINO KATSUHIKO , SOGOU SABUROU
IPC分类号： G06F7/64
摘要： PURPOSE:To obtain a maximum value with a high precision automatically and easily, by detecting that an input value is 0 or the code is changed in the integrator of a digital differentiator. CONSTITUTION:An input value from an integrator and a preceding value 9 are discriminated by an extreme value discriminating circuit 10; and if the input value 4 is 0 or has a sign different from that the preceding value 9, a strobe is outputted to a digital comparator 12. An absolute value circuit 11 operates the absolute value of an output 7 of an Y-register 6 and outputs it to the digital comparator 12. The output of a memory 14 which is the absolute value of the preceding extreme value is compared with the output of the absolute value circuit 11; and if the latter is larger, the value of the absolute value circuit 11 is written to the memory 14, and a write signal 15 is outputted to a memory 16 to store the value 7 of the Y-register in the memory 16.

9. 发明专利

JPS5767985A Graphic display indicating system 失效
标题翻译：图形显示指示系统
公开(公告)号：JPS5767985A
公开(公告)日：1982-04-24
申请号：JP14294780
申请日：1980-10-15
申请人： Hitachi Electronics
发明人： HIBINO KATSUHIKO , JIYOU AKIO , ISHII SHIGERU
IPC分类号： G09G1/16 , G09G1/00 , G09G1/06 , G09G5/36

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