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6. 发明专利

JPH059645B2 失效
公开(公告)号：JPH059645B2
公开(公告)日：1993-02-05
申请号：JP22786385
申请日：1985-10-15
申请人： HITACHI CONSTRUCTION MACHINERY
发明人： WATANABE HIROSHI , IZUMI EIKI , ICHAMA SHUICHI , AOYANAGI YUKIO , UNO KEIICHIRO , YASUDA TOMOHIKO
IPC分类号： F15B11/05 , E02F3/43 , E02F9/20 , E02F9/22 , F15B11/08

7. 发明专利

JPH0425427B2 失效
公开(公告)号：JPH0425427B2
公开(公告)日：1992-04-30
申请号：JP12384384
申请日：1984-06-18
申请人： HITACHI CONSTRUCTION MACHINERY
发明人： TANAKA YASUO , IZUMI EIKI , ISHIZUKA KATSUAKI
IPC分类号： F02D41/14 , E02F9/22 , F02D29/04 , F02D41/08 , F02D41/40 , F04B49/00 , F04B49/06 , F04B49/08

9. 发明专利

JPH03209160A GATE CIRCUIT FOR ULTRASONIC FLAW-DETECTOR 失效
公开(公告)号：JPH03209160A
公开(公告)日：1991-09-12
申请号：JP253090
申请日：1990-01-11
申请人： HITACHI CONSTRUCTION MACHINERY
发明人： AOKI SHIGENORI , IZUMI EIKI , TANAKA YASUO
IPC分类号： G01N29/38 , G01N29/04 , G01N29/22
摘要： PURPOSE:To exactly display a defective position by detecting the maximum value of data existing in the period during a gate timing signal specifying the time range is outputted and latching the value of an address counter at that time. CONSTITUTION:A gate signal generating circuit 22 is furnished with a memory 22a for timing process, wherein addresses corresponding to each sampling are provided and the data for one bit are stored. The addresses of memory 22a are specified in order by the address counter 22b, and an FF 22c is operated in accordance with the output data of memory 22a. When the start time and finish time of the time range to be inspected are set, the gate timing signal is outputted at the start time and stopped at the finish time. The maximum value among the data subjected to make an A/D conversion during this output period, is detected, and the value of address counter at the time when this maximum value is detected is latched and this value indicates the defective position; therefore, the defective position can be exactly obtained.

10. 发明专利

JPH03209159A GATE CIRCUIT FOR ULTRASONIC FLAW-DETECTOR 失效
公开(公告)号：JPH03209159A
公开(公告)日：1991-09-12
申请号：JP252990
申请日：1990-01-11
申请人： HITACHI CONSTRUCTION MACHINERY
发明人： TANAKA YASUO , IZUMI EIKI , AOKI SHIGENORI
IPC分类号： G01N29/38 , G01N29/04 , G01N29/22
摘要： PURPOSE:To exactly display the height of echo signal within the inspection range by specifying the time range of start and finish according to a gate timing signal and detecting the maximum value among data existing in the period during this signal is outputted. CONSTITUTION:A contact probe is excited by a transmission part in accordance with a trigger signal of timing circuit 8, and the received echo signal is converted to a digital value with a specified sampling cycle by an A/D converter 5 and outputted to a waveform memory and gate circuit 21, and addresses of the data stored in the waveform memory are successively specified by an address counter 7. At this time, the gate circuit 21 is constituted of a gate signal generating circuit 22 and maximum value detecting circuit 23, and the gate signal for the purpose of extracting the echo signal only in the inspecting range for an object to be inspected is generated by the circuit 22, and the maximum value of echo signal which is inputted in the gate period formed in the circuit 22 is detected by the circuit 23. By such an arrangement, the size of defect can be exactly detected.

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