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1. 发明专利

JPH04246686A DRIVING CIRCUIT FOR MATRIX DISPLAY DEVICE 失效
公开(公告)号：JPH04246686A
公开(公告)日：1992-09-02
申请号：JP1127991
申请日：1991-01-31
申请人： HITACHI CHEMICAL CO LTD , HITACHI LTD
发明人： INOUE FUMIO , YOSHIDA TAKESHI , ONO YOSHIMASA , KOSAKA MASAHIRO
IPC分类号： G09G3/20 , G09G3/30
摘要： PURPOSE:To decrease the number of driver ICs in use and to use only one high-voltage power source to drive column-side and row-side electrodes. CONSTITUTION:Driver ICs 4, 2, and 3 of function constitution including switching circuits having a push-pull function are provided on the column-side and row-side electrodes of a thin film EL panel 1. The pull-up side common line of the drier IC 4 is connected to a positive modulation power source through a switch (diode 8) and the pull-down side common line is connected to a negative modulation power source through a switch 11; and the pull-up side common lines of the driver ICs 2 and 3 are connected to the positive modulation power source through a switch 9, a write power source, and a switch 10 and the pull-down side common lines are connected to a reference potential.

2. 发明专利

JP2014091858A Pretreatment agent for electroless plating and production method thereof 审中-公开
标题翻译：电沉积预处理剂及其生产方法
公开(公告)号：JP2014091858A
公开(公告)日：2014-05-19
申请号：JP2012243647
申请日：2012-11-05
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： ITO AKIKO , INOUE FUMIO , HATAKEYAMA SHUICHI , YAMAMOTO HIROSHI
IPC分类号： C23C18/20
摘要： PROBLEM TO BE SOLVED: To provide a pretreatment agent for electroless plating suitable for a cleaning conditioning step performed prior to an electroless plating process.SOLUTION: A pretreatment agent for electroless plating in one embodiment contains (A) a surfactant having a cloud point of 70°C or higher and a surface tension of 34-44 dyn/N, and (B) a surfactant having a cloud point of 50-75°C and a surface tension of 30-33 dyn/N, and the (A)component and the (B)component are each at least one kind selected from a group comprising alkyl ether type nonionic surfactants and alkyl phenyl ether type nonionic surfactants.
摘要翻译：要解决的问题：提供适用于化学镀处理之前进行的清洁调理步骤的化学镀的预处理剂。解决方案：在一个实施方案中，用于无电镀的预处理剂包含（A）浊点为70的表面活性剂 ℃以上，表面张力为34-44dyn / N，（B）表面活性剂的浊点为50-75℃，表面张力为30-33dyn / N，（A）成分和（B）成分各自为选自烷基醚型非离子表面活性剂和烷基苯基醚型非离子表面活性剂中的至少一种。

3. 发明专利

JP2013023766A Surface treatment method for conductive base material for mounting tape carrier-fitted semiconductor, conductive base material for mounting tape carrier-fitted semiconductor obtained by using the treatment method, and semiconductor package 审中-公开
标题翻译：用于安装带状载体半导体的导电基材的表面处理方法，用于使用处理方法获得的用于安装带状载体的半导体的导电基材和半导体封装
公开(公告)号：JP2013023766A
公开(公告)日：2013-02-04
申请号：JP2011163092
申请日：2011-07-26
申请人： Hitachi Chemical Co Ltd , 日立化成工業株式会社
发明人： INOUE FUMIO , YAMASHITA TOMOAKI , HIROYAMA YUKIHISA , SAKAYORI KAZUHIKO
IPC分类号： C23F1/18 , H01L23/12 , H01L23/28 , H01L23/50
CPC分类号： H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide: a surface treatment method for a conductive base material for mounting a tape carrier-fitted semiconductor which can improve reliability and adhesive properties with a sealing material; a conductive base material for mounting a tape carrier-fitted semiconductor obtained by using the treatment method; and a semiconductor package obtained by using them.SOLUTION: The surface treatment method for a conductive base material for mounting a tape carrier-fitted semiconductor includes a first roughening step of bringing a conductive base material for mounting a tape carrier-fitted semiconductor into contact with a first chemical roughening liquid including a corrosion inhibitor to form a roughened shape on the surface of the conductive base material for mounting a semiconductor. The surface treatment method for a conductive base material for mounting a tape carrier-fitted semiconductor further includes a second roughening step of bringing the same into contact with a second chemical roughening liquid including a corrosion inhibitor after the first roughening step. The conductive base material for mounting a tape carrier-fitted semiconductor is obtained by using the surface treatment. The semiconductor package is obtained by using them.
摘要翻译：要解决的问题：提供一种用于安装带状载体配合半导体的导电性基材的表面处理方法，其能够利用密封材料提高可靠性和粘合性; 用于安装通过使用所述处理方法获得的带状载体配合半导体的导电基材; 以及通过使用它们获得的半导体封装。解决方案：用于安装带状载体安装半导体的导电基材的表面处理方法包括：第一粗糙化步骤，将用于安装载带配合半导体的导电性基材与第一化学粗糙化液接触，所述第一化学粗糙化液包括在用于安装半导体的导电性基材的表面上形成粗糙化形状的腐蚀抑制剂。用于安装带状载体半导体的导电基材的表面处理方法还包括在第一粗糙化步骤之后使其与含有腐蚀抑制剂的第二化学粗糙化液接触的第二粗糙化步骤。通过使用表面处理获得用于安装带状载体配合半导体的导电性基材。通过使用半导体封装。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2002237547A SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD, AND SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD 失效
公开(公告)号：JP2002237547A
公开(公告)日：2002-08-23
申请号：JP2001033172
申请日：2001-02-09
申请人： HITACHI CHEMICAL CO LTD
发明人： MORIIKE MICHIO , INOUE FUMIO , AWANO YASUHIKO , YAMAGUCHI REIKO , TSUBOMATSU YOSHIAKI
IPC分类号： H01L23/12 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To provide a substrate suited for the small size and high density use and having superior reliability, by preventing a crack in package for a small semiconductor package and its manufacturing method, and to provide the semiconductor package and its manufacturing method. SOLUTION: The substrate is composed of at least a conductive pattern, connected to a semiconductor chip and an insulating base for supporting the conductive pattern. The substrate for the package has a stopping hole, which does not reach the side of the conductive pattern, on a face opposite to the conductive pattern and at the outer side of an area for mounting the semiconductor chip in the insulating base.

5. 发明专利

JP2002185110A SUBSTRATE AND SEMICONDUCTOR PACKAGE USING IT 失效
公开(公告)号：JP2002185110A
公开(公告)日：2002-06-28
申请号：JP2000383813
申请日：2000-12-18
申请人： HITACHI CHEMICAL CO LTD
发明人： KAWAKAMI YUTAKA , INOUE FUMIO , AWANO YASUHIKO , SHIMIZU AKIRA , NAMATAME KAZUHIKO
IPC分类号： H05K3/28 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a substrate which can exceedingly suppress the disconnection of wiring caused by the cracking of a solder resist, and to provide a semiconductor package using the substrate. SOLUTION: The substrate has terminals for connecting solder balls. The wiring connected to the terminals has a width of

6. 发明专利

JP2002176124A BOARD FOR MOUNTING SEMICONDUCTOR, SEMICONDUCTOR PACKAGE USING THE BOARD, AND MANUFACTURING METHOD BOTH THEREOF 失效
公开(公告)号：JP2002176124A
公开(公告)日：2002-06-21
申请号：JP2000370865
申请日：2000-12-06
申请人： HITACHI CHEMICAL CO LTD
发明人： INOUE FUMIO , NAKAMURA HIDEHIRO , AWANO YASUHIKO , ENOMOTO TETSUYA , YAMAGUCHI REIKO , MORIIKE MICHIO , ENDO TOSHIHIRO , TSUBOMATSU YOSHIAKI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a low-cost semiconductor mounting board for reducing the diameter of a bent hole, along with a semiconductor package by using the semiconductor mounting board, and to provide the methods for manufacturing the semiconductor mounting board and the semiconductor package. SOLUTION: The semiconductor mounting board in the semiconductor package includes an insulating base, a connection terminal passing the insulating base, and a plurality of conductive patterns on at least one side of the insulating base. One or more conductive patterns are connected to the connection terminal, and the semiconductor mounting board has a hole, in which a space formed between the conductive pattern and a semiconductor-chip mounting insulating adhesive on the rear of the semiconductor chip up to the rear face thereof when a semiconductor chip is mounted on the conductive pattern is passed through to the rear face of the insulating base.

7. 发明专利

JP2002118203A SUBSTRATE FOR MOUNTING SEMICONDUCTOR, MANUFACTURING METHOD THEREFOR, SEMICONDUCTOR PACKAGE EMPLOYING THE SAME AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2002118203A
公开(公告)日：2002-04-19
申请号：JP2000311062
申请日：2000-10-11
申请人： HITACHI CHEMICAL CO LTD
发明人： YAMAGUCHI REIKO , INOUE FUMIO , AWANO YASUHIKO , TSUBOMATSU YOSHIAKI , IWASAKI YORIO , OHATA HIROTO
IPC分类号： H01L23/12 , H01L23/14
摘要： PROBLEM TO BE SOLVED: To provide a small semiconductor package which is excellent in miniaturization, densification, and also excellent in reliability by preventing the package from cracking and a substrate for mounting a semiconductor, and to provide an efficient method for manufacturing the substrate for mounting the semiconductor and a method for manufacturing the semiconductor package. SOLUTION: The substrate for mounting the semiconductor comprises a flexible insulating base material and a wiring conductor, and the base material has low moisture permeability. Thus, the efficient method for manufacturing the substrate for mounting the semiconductor and the method for manufacturing the semiconductor package can be obtained.

8. 发明专利

JP2002110858A SEMICONDUCTOR PACKAGE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002110858A
公开(公告)日：2002-04-12
申请号：JP2001237791
申请日：2001-08-06
申请人： HITACHI CHEMICAL CO LTD
发明人： FUKUTOMI NAOKI , TSUBOMATSU YOSHIAKI , INOUE FUMIO , YAMAZAKI AKIO , OHATA HIROTO , HAGIWARA SHINSUKE , TAGUCHI NORIYUKI , NOMURA HIROSHI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor package substrate that can cope with the high integration of a semiconductor. SOLUTION: In an insulating support, a plurality of sets of wiring 2 are formed on one side, an LSI chip 3 is packaged in a polyimide film 20 where an opening is provided at a place where a soldering pole 7 that is an external connection terminal is formed in the wiring 2 for forming a through hole for the soldering pole 7 via a die-bonding tape 4' for allowing the LSI chip 3 to be continuous to the plurality of sets of wiring 2, the LSI chip 3 is sealed by resin 5, the soldering pole 7 that is continuous to the wiring 2 is formed in the through hole, and the polyimide film 20 is stamped out by a die for dividing into each package.

9. 发明专利

JP2002026086A CONNECTING METHOD FOR BOARD; MANUFACTURING METHODS USING THE CONNECTING METHOD AND FOR MANUFACTURING WIRING BOARD, BOARD FOR SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE; AND WIRING BOARD, BOARD FOR SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JP2002026086A
公开(公告)日：2002-01-25
申请号：JP2000209968
申请日：2000-07-11
申请人： HITACHI CHEMICAL CO LTD
发明人： ENOMOTO TETSUYA , NAKAMURA HIDEHIRO , INOUE FUMIO , AWANO YASUHIKO , YAMAGUCHI REIKO , NAGAI AKIRA , TAKEUCHI KAZUMASA
IPC分类号： H05K3/32 , H01L21/60 , H01L21/607
摘要： PROBLEM TO BE SOLVED: To provide a connecting method for boards whereby a small connection resistance and a high connection reliability are obtained. SOLUTION: A connecting method for boards wherein two boards having their connection terminals are pressed on each other while opposing their connection terminals to each other and applying to one of them an ultrasonic vibration in its surface direction; manufacturing methods using the connecting method and for manufacturing a wiring board, a board for semiconductor packages, and a semiconductor package; and the wiring board, the board for semiconductor packages, and the semiconductor package which are manufactured by the manufacturing methods.

10. 发明专利

JP2001217351A CHIP SUPPORT BOARD FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE USING IT, AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001217351A
公开(公告)日：2001-08-10
申请号：JP2000027173
申请日：2000-01-31
申请人： HITACHI CHEMICAL CO LTD
发明人： INOUE FUMIO , TSUBOMATSU YOSHIAKI , OHATA HIROTO , AWANO YASUHIKO , IWASAKI YORIO
IPC分类号： H01L23/14 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a chip support board for a semiconductor package, a semiconductor package using it, and its manufacturing method of less deflection, excellent in external connection reliability. SOLUTION: An insulating support board comprising at least three layers, namely a first layer, a second layer, and a third layer starting on the side where a metal wiring is formed, is provided. With thicknesses and thermal expansion factors of the layers as (T1, α1), (T2, α2), (T3, α3) in order, (T1/T2) as well as (T3/T2)

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