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    • 2. 发明专利
    • Processor
    • 处理器
    • JP2007156940A
    • 2007-06-21
    • JP2005352895
    • 2005-12-07
    • Fujitsu Ltd富士通株式会社
    • SAITO HIROYUKINISHITOI TAKESHI
    • G06F9/50
    • G06F11/18G06F11/3433G06F15/16G06F2201/81G06F2201/87
    • PROBLEM TO BE SOLVED: To provide a technology capable of improving execution speed and failure proof of transaction of a CPU. SOLUTION: A transaction input/output CPU 11 outputs an execution result of transaction to inputted processing to be executed. A plurality of processing CPU 12 execute the transaction according to an instruction from the transaction input/output CPU 11. A plurality of memories 13 and 14 are associated with the respective processing CPU 12 and store the transaction inputted to the transaction input/output CPU 11 or the result of execution. A register 16 stores a pointer indicating an address common among the plurality of memories 13 and 14. The processing CPU 12 read the pointer from the register 16, read the transaction from a stored party of the transaction in the memory 13 associated with the respective CPU 12, and execute it. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供能够提高CPU的执行速度和故障证明的技术。 解决方案:交易输入/输出CPU11将执行的执行结果输出到要执行的输入处理。 多个处理CPU 12根据来自交易输入/输出CPU 11的指令执行交易。多个存储器13和14与相应的处理CPU 12相关联并且存储输入到交易输入/输出CPU 11的交易 或执行结果。 寄存器16存储指示多个存储器13和14中共同的地址的指针。处理CPU 12从寄存器16读取指针,从与相应CPU相关联的存储器13中的事务的存储方读取事务 12,并执行。 版权所有(C)2007,JPO&INPIT