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    • 6. 发明专利
    • EQUALIZING CIRCUIT
    • JPS6398233A
    • 1988-04-28
    • JP24359386
    • 1986-10-14
    • FUJITSU LTD
    • NAKAZAWA ISAOKURIHARA HIROSHI
    • H03H7/01H03H11/04H04B3/06H04J3/06
    • PURPOSE:To constitute an equalization circuit without using the equalization circuit having complicated reverse characteristic of a transmission line, by producing a wave with double the carrier to be modulated, generating the same quantity of distortion as that of the transmission line, and negating the quantity of distortion. CONSTITUTION:A modulation signal is inputted to a modulation circuit 100, and it is transmitted on the transmission line 101 having a prescribed transmission characteristic, and a double wave is generated at a double wave generation circuit 1, and the same quantity of distortion as that of distortion received by the transmission characteristic is generated. And an output frequency is reduced at a frequency conversion circuit 7, and its output signal and the output signal of the double wave generation circuit 1 are mixed at a mixer 3, and a modulation factor is restored, then, the distortion is negated. In such way, it is possible to satisfactorily compensate the distortion generated on a transmission line characteristic.
    • 7. 发明专利
    • LINE SUPERVISORY SYSTEM
    • JPS61285836A
    • 1986-12-16
    • JP12787585
    • 1985-06-12
    • FUJITSU LTD
    • NAKAZAWA ISAO
    • H04L1/00H04J1/16
    • PURPOSE:To use a filter with a comparatively low Q as a filter extracting a subcarrier by using a code signal as a signal superimposed on the subcarrier used for line supervision so as to decrease sufficiently the frequency of noise generation being causes of an error to the code signal. CONSTITUTION:A code signal generated as a digital signal with a predetermined pattern in advance at both transmission and reception ends by a code signal generator 6 at the transmission side 1 modulates the carrier of the frequency of upper band of a main signal by a digital modulator 5, an output from the digital modulator 5 is subjected to frequency multiple with the main signal by a hybrid circuit 4 and the result is sent from a transmission section 3. In this case, a filter with a comparatively low Q is used and even if a noise is mixed in the output of the filter, the error in the code signal is comparatively less. Since the line supervision is easy and the line is supervised by a one-bit the error of 10 is discriminated in a short time such as 100musec, when the clock frequency of the digital signal is selected as 1MHz.
    • 8. 发明专利
    • SINGLE ENDED PUSH-PULL AMPLIFIER CIRCUIT
    • JPS60121805A
    • 1985-06-29
    • JP22905483
    • 1983-12-06
    • FUJITSU LTD
    • NAKAZAWA ISAOKIYONO HIDEKI
    • H03F3/30H03F3/20H03F3/213
    • PURPOSE:To prevent frequency characteristics to a low frequency input signal from deteriorating as to a single ended push-pull amplifier circuit by using a resistor only for both the formation of an in-phase current corresponding to an input signal and the setting of a DC bias voltage. CONSTITUTION:The single ended push-pull SEPP amplifier circuit has a resistance R1 connected between the collector of a transistor TRQ1 and a +V power source and a resistance R5 between the collector and base of the TRQ1 to constitute a parallel feedback amplifier circuit A1, and a resistance R2 is connected between the emitter of a TRQ2 and a -V power source to constitute a common emitter type amplifying circuit A2. An input terminal I2 is connected to the base of the TRQ2, and an output terminal O2 is connected to the collector of the TRQ1; and a resistance R6 is connected between outputs of circuits A1 and A2, and a resistance R7 is connected between the base of the TRQ1 and the collector of the TRQ2. The resistances R1, and R6-R7 are selected to put the emitter current i1 of the TRQ1 and the collector current i2 of the TRQ2 in phase and equalize their levels, and also to satisfy the bias condition of the SEPP amplifier circuit, thereby obtaining the amplifier circuit with excellent frequency characteristics.
    • 9. 发明专利
    • PICTURE SIGNAL TRANSMISSION SYSTEM
    • JPS60117978A
    • 1985-06-25
    • JP22569383
    • 1983-11-30
    • FUJITSU LTD
    • NAKAZAWA ISAO
    • H04K1/00H04N7/167H04N7/169
    • PURPOSE:To avoid easy detection of picture signals and to keep satisfactorily the privacy with a system where the variation amount of a certain time difference from the picture signal is transmitted, by giving the digital control to said time difference. CONSTITUTION:Both horizontal and vertical synchronizing signals are detected at a horizontal/vertical synchronizing signal detecting part 1 for some of picture signals applied to an input terminal 5. A delay time control circuit 2 detects the order of the picture signal according to the input horizontal synchronizing signal. While the delay amount of a variable delay circuit 3 is previously decided in response to each horizontal synchronizing signal. The circuit 3 is controlled to obtain the prescribed delay time. The rest part of the picture signals supplied to the terminal 5 receives a delay from the circuit 3 and is supplied to another terminal of a differential amplification part 4 and scrambled to be delivered through a terminal 6 after the difference calculated to the picture signal supplied directly. At the reception side some of the reception signals supplied to a terminal 13 undergoes detection for both horizontal and vertical synchronizing signals through a horizontal/vertical synchronizing signal detecting part 7. Thus a variable delay circuit 10 performs the control exactly equal to that of the transmission side with use of both detected horizontal and vertical synchronizing signals.
    • 10. 发明专利
    • FREQUENCY DIVISION CIRCUIT
    • JPS6025325A
    • 1985-02-08
    • JP13374283
    • 1983-07-22
    • FUJITSU LTD
    • NAKAZAWA ISAO
    • H03K23/64H03K27/00
    • PURPOSE:To prevent generation of noise and effect due to ambient temperature by charging a capacitor with an output from a phase comparator circuit and discharging the capacitor with a signal from an N counter circuit to control a delay time thereby constituting the circuit of only a circuit suitable for circuit integration. CONSTITUTION:M-set of input pulse signals are counted by an M counter circuit C-3. On the other hand, the input pulse signal passing through a variable delay circuit VD is counted by N-pulses at an N counter circuit C-4. A voltage corresponding to the phase difference is outputted by a phase comparator circuit PD from an output of both the counter circuits. An integration circuit I charges a cpacitor with an output from the circuit PD and the electric charge stored in the capacitor is discharged by a signal of the N-count end of the circuit C-4. The output from the circuit I controls the delay time of the variable delay circuit VD.