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1. 发明专利

JPS5873265A RING TRIP SYSTEM 失效
公开(公告)号：JPS5873265A
公开(公告)日：1983-05-02
申请号：JP17241881
申请日：1981-10-28
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： HASEGAWA KENZOU , OIKAWA YOSHINORI , ARAI TOSHIO , HASEGAWA KOUICHI , SATOU HIDEHIRO
IPC分类号： H04M3/02
摘要： PURPOSE:To attain DC supply feeding, by triggering of the detection of response of the called party, and transmitting in the earthing transmission mode, and releasing the transmission of callout signal quickly without the state of current interruption on a subscriber line after the response of a called party at the callout singal transmission. CONSTITUTION:The circuitry is constituted that callout signal transmission switches S1-S4, especially the earthing transmission switch S2, are used, the detection of response of a called party 1 is taken as a trigger to immediately obtain the earthing transmission mode, and a ringing signal (CR) is disconnected without the interruption of current to a subscriber line, through the hardware configuration. The line B battery/line A earthing mode is set off through the callout signal release command from the software to obtain a DC feeding mode (line B earthing/line A battery). Especially, a ring trip 3 detects the potential difference across a resistor R2 and monitors the response of the called party with the output of ring trip.

2. 发明专利

JPS58112424A POWER SOURCE NOISE SUPPRESSING SYSTEM 失效
公开(公告)号：JPS58112424A
公开(公告)日：1983-07-04
申请号：JP21031381
申请日：1981-12-25
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： IMAI MASAMICHI , TATSUNO HIDEO , SATOU HIDEHIRO , SHIRAISHI OSAMU , SHINKAWA HIROSHI
IPC分类号： H02J1/02

3. 发明专利

JPS5893391A POWER ON RESET SYSTEM FOR ELECTRONIC CIRCUIT PACKAGE 失效
公开(公告)号：JPS5893391A
公开(公告)日：1983-06-03
申请号：JP19249981
申请日：1981-11-30
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： SHIBATA TOMOHIKO , KOINUMA TAKEO , HANDA TOORU , SATOU HIDEHIRO , YOSHINO HARUYUKI
IPC分类号： H05K1/11 , H03K3/02 , H03K17/22 , H05K1/02

4. 发明专利

JPS58221555A Talkie transmitting system 失效
标题翻译： TALKIE发送系统
公开(公告)号：JPS58221555A
公开(公告)日：1983-12-23
申请号：JP10484382
申请日：1982-06-18
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： KAWASAKI ICHIO , TAKEI AKIRA , OONO MASAHIKO , SATOU HIDEHIRO , YOSHINO HARUYUKI
IPC分类号： H04M3/50 , H04Q11/04
CPC分类号： H04Q11/04
摘要： PURPOSE:To transmit the talkie to all subscribers without lowering the traffic capacity for a subscriber line concentrator of a time-division telephone switchboard, by providing a talkie exclusive highway. CONSTITUTION:A time slot having a non-call pattern of a distribution highway 4 is usually connected to a talkie circuit 130 via a line concentration switch 301, and no audio signal is delivered to the output of the circuit 130. When it is required to transmit the talkie to a subscriber 10b of a low call factor in an abnormal congestion mode, a time slot having a digital talkie signal pattern of the highway 4 is connected to the circuit 130 with switching of connection of the switch 301. Then the analog talkie signals are transmitted to all subscribers 10b from the circuit 130. At the same time, the talkie signal is individually transmitted when necessary to a subscriber 10a of high call factor with connection of the switch 301. As a result, a function concentrating part 123 is not needed within a circuit 120 for subscriber 10b. This never lowers the traffic capacity.
摘要翻译：目的：通过提供对讲机专用公路，将对讲机发送给所有用户，而不降低时分电话交换机的用户线集线器的流量。构成：具有分配公路4的非呼叫模式的时隙通常经由线路集中开关301连接到对讲电路130，并且没有音频信号被传送到电路130的输出。当需要在异常拥塞模式下将对讲机发送到低呼叫因子的用户10b，具有公路4的数字对讲机信号模式的时隙通过开关301的连接切换连接到电路130.然后模拟对讲机信号从电路130发送到所有订户10b。同时，当需要时，对讲机信号被单独发送到具有开关301的连接的高呼叫系数的用户10a。结果，功能集中部分123是在用户10b的电路120内不需要。这样就不会降低流量。

5. 发明专利

JPS60132414A LEVEL DECIDING CIRCUIT 失效
公开(公告)号：JPS60132414A
公开(公告)日：1985-07-15
申请号：JP23977283
申请日：1983-12-21
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HASHIMOTO MAKOTO , SATOU HIDEHIRO , KIMURA TADAKATSU , IMAGAWA HITOSHI
IPC分类号： H03K19/0948 , H03K3/3565 , H03K17/22
摘要： PURPOSE:To ensure the correct actuation of a level deciding circuit even in case the noises are superposed on the input signal, by connecting the 4th MOS transistor (TR) in parallel to one of the 1st-3rd MOS transistors put on each other and then turning on and off the 4th transistor. CONSTITUTION:An MOSTR10 is connected in parallel to an MOSTR9 among those MOSTRs 7-9 which are put on each other, and the outputs of TRs 7 and 8 are connected to the gates of MOSTRs 11 and 12 as well as a terminal 6. The outputs of TRs 11 and 12 are connected to a control signal input terminal 13 to control the TR10. The control signal to be applied to the terminal 13 is selected so that the TR10 is turned off when the input signal of a terminal 5 has a low level. Then the TR10 is turned on when the input signal is set at a level higher than the threshold voltage decided by TRs 7-9. When the input level is low and the TR10 is kept off, the TR8 is set at a level higher than a ground level. At the same time, the threshold voltage of a level deciding circuit 4 is set at a high level VT1. When the input level rises up and exceeds the level VT1, the TR10 is turned on. Then a terminal 6 is changed to an L level from an H level, and the threshold level of the circuit 4 is reduced down to the voltage VT2. Thus the circuit 4 has the hysteresis characteristics.

6. 发明专利

JPS57129020A SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS57129020A
公开(公告)日：1982-08-10
申请号：JP1428681
申请日：1981-02-04
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAKIDO KAZUO , SATOU HIDEHIRO , FUJII FUMIAKI , UCHIMURA KUNIHARU
IPC分类号： H03M1/08 , H04B14/04 , H03K13/00
摘要： PURPOSE:To reduce SN ratio, by providing a gate means by which a clock pulse of a comparatively high speed supplied to an external input terminal is made to a direct input signal, and operating a digital signal system circuit by the time required essentially, by the clock pulse selected by this gate means. CONSTITUTION:When a synchronizing pulse is inputted and the 9th input of a PCM output clock pulse is counted by a counting circuit 32, the subsequent input of the PCM clock pulse to all logical circuits excluding an input protecting circuit excluding an input protecting circuit 22 is inhibited automatically until a rise edge of the next synchronizing pulse is inputted. In this way, since all the logical circuits excluding the input protecting circuit 22 are made to a nonoperation state, generation of a digital noise from a PCM output controlling circuit 10 is suppressed. Also, since the SN ratio can be reduced, a change to IC is executed easily.

7. 发明专利

JPS59160776A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS59160776A
公开(公告)日：1984-09-11
申请号：JP3457983
申请日：1983-03-04
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： MIKAMI YASUO , SATOU HIDEHIRO , IMAGAWA HITOSHI , UEHARA HIROYASU
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/2884
摘要： PURPOSE:To make a set signal terminal usable for other purposes during test mode by the circuits which decides the test mode under working. CONSTITUTION:An input terminal 1 is used for a power only set signal. deciding circuits 6, 7 detect the change in the voltage of an input signal. The output from an inverter 9 is applied as it is to an internal circuit in the normal stage but it is inconvenient if a power on reset signal is generated in the inverter 9 in the test mode and therefore the output of the inverter 9 and the output from the circuit 6 are ORed by an OR gate 10. Then the terminal 1 is made usable for inputting the change-over signal for the test mode while the internal circuit is kept operated normally in the test mode.
摘要翻译：目的：在测试模式下，通过决定测试模式工作的电路，使设置的信号端子可用于其他目的。构成：输入端子1用于电力设定信号。判定电路6,7检测输入信号的电压的变化。逆变器9的输出原样应用于内部电路，但是如果在测试模式下在逆变器9中产生上电复位信号，则逆变器9的输出和输出电路6由或门10进行或运算。然后，在测试模式下内部电路保持正常工作的情况下，端子1可用于输入用于测试模式的转换信号。

8. 发明专利

JPS5858618A CONSTANT-VOLTAGE CIRCUIT 失效
公开(公告)号：JPS5858618A
公开(公告)日：1983-04-07
申请号：JP15482181
申请日：1981-10-01
申请人： HITACHI LTD
发明人： SATOU HIDEHIRO
IPC分类号： G05F3/24
摘要： PURPOSE:To exactly perform a power-down function, by adding two MOS transistors (TR) whose polarity is different, to a conventional constant-voltage circuit, and also constituting the conventional constant-voltage circuit when power-down is not performed, by said addition. CONSTITUTION:When generating a power-down output, a power-down signal is applied to a terminal 19 in order that an MOS TR 17 is turned on, and a MOS TR 18 is turned off. As a result, the TR 17 is turned on, and the TR 18 is turned off. As a result, the gates of TRs 4 and 5 are connected, also the TRs 4 and 5 are connected in series, the gate and the drain of the TRs 4 and 5 become an open state which is not short-circuited, and its circuit configuration is constituted of a CMOS invertor. In this case, as a result of the fact that the TR 17 has been turned on, the TR 5 also conducts, an output terminal 3 becomes nearly ground potential 2, the potential of the output terminal 3 becomes nearly ground potential, a TR 10 is turned off, and the power is cut off.

9. 发明专利

JPS5775029A Decoder 失效
标题翻译：解码器
公开(公告)号：JPS5775029A
公开(公告)日：1982-05-11
申请号：JP15075080
申请日：1980-10-29
申请人： Hitachi Ltd
发明人： SATOU HIDEHIRO , YAMAKIDO KAZUO
IPC分类号： H03M1/66 , H03M1/38 , H03M1/80 , H04B14/04
CPC分类号： H03M1/80
摘要： PURPOSE:To obtain a decoder having a prescribed nonlinearity, by setting the ratio of the overall capacity value of a capacitor array circuit to the capacity value of the hold capacitor of a sample holding circuit to a prescribed value. CONSTITUTION:A reset switch RS2 is closed to discharge a hold capacitor CH, and next, a set switch ST is connected to an input terminal VIN and a sampling switch SP is closed. An input voltage is divided and applied to capacitors C1- C8, and switches S1-S8 are controlled selectively by a PCM code. At this time, when the overall capacity value of capacitors C1-C8 is denoted as Ca, the gain of a sample holding circit is GSH= Ca/CH. Since Ca=256C is true, CH is 251C/alpha approximately in case of the mu rule and is 252C/alpha in case of the A rule. However, alpha is 1 practically.
摘要翻译：目的：通过将电容器阵列电路的总电容值与采样保持电路的保持电容的容量值的比例设定为规定值，来获得规定的非线性的解码器。构成：复位开关RS2闭合以放电保持电容CH，接下来，将一个开关ST连接到输入端VIN，并且采样开关SP闭合。输入电压被分压并施加到电容器C1-C8，开关S1-S8由PCM代码选择性地控制。此时，当电容器C1-C8的总容量值表示为Ca时，样品保持环路的增益为GSH = Ca / CH。由于Ca = 256℃是真的，在μ规则的情况下，CH约为251C /α，在A规则的情况下为252C /α。然而，alpha实际上是1。

10. 发明专利

JPS59161160A Transient response protecting system 失效
标题翻译：瞬态响应保护系统
公开(公告)号：JPS59161160A
公开(公告)日：1984-09-11
申请号：JP3458283
申请日：1983-03-04
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SATOU HIDEHIRO , ISHIZAWA AKIRA
IPC分类号： H04M3/02 , H04M19/02
CPC分类号： H04M19/026
摘要： PURPOSE:To prevent a malfunction by the transient characteristic of a low-pass filter by adding a switching circuit and a timing circuit, and suppressing the input signal of a ringing trip circuit when switching a call signal. CONSTITUTION:A timing generating circuit 8 is provided on a transient response protecting system, a pulse of a prescribed pulse width is generated in response to a control signal 100 of a call signal, and a switching circuit 9 is controlled by its pulse. By switching this circuit 9, one of signal detecting resistances 5a, 5b connected between a signal converting circuit 2 and a low-pass filter circuit 6 is short-circuited, and an input signal level to the filter circuit 6 is suppressed. In this way, a malfunction by the transient characteristic of the filter circuit 6 is prevented, and an operation in case of switching a call signal is made stable.
摘要翻译：目的：通过添加开关电路和定时电路来防止低通滤波器的瞬态特性的故障，并且在切换呼叫信号时抑制振铃跳闸电路的输入信号。构成：定时发生电路8设置在瞬态响应保护系统上，响应于呼叫信号的控制信号100产生规定脉冲宽度的脉冲，并且切换电路9由其脉冲控制。通过切换该电路9，连接在信号转换电路2和低通滤波器电路6之间的信号检测电阻5a，5b之一被短路，并且抑制了对滤波电路6的输入信号电平。以这种方式，可以防止由过滤电路6的瞬变特性引起的故障，并且使呼叫信号切换的情况下的操作稳定。

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