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1. 发明专利

JPS5597647A FAULT MONITOR SYSTEM FOR MULTIIPROCESSOR CONTROL SYSTEM 失效
公开(公告)号：JPS5597647A
公开(公告)日：1980-07-25
申请号：JP448079
申请日：1979-01-20
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： OSANAI YOSHIHIRO , YAMADA TAKAHIKO , TAGUCHI TSUNEO , TOKITA YOSHIAKI , ENDOU KAZUMI
IPC分类号： G06F15/16 , G06F11/00 , G06F15/00 , G06F15/177 , H04M3/22 , H04Q3/545
摘要： PURPOSE:To increase both the reliability and the working efficiency of the system by giving the fault announcement of the master processor to the switch circuit in case some fault occurs and then switching one of the slave processors to the master processor. CONSTITUTION:One of several processors CP is used as the master processors, and others are used as the slave processors. Thus the proces request signals are delivered from the master processor with every fixed timing, and the slave processor received the signal returns the answer to the master processor. In such way, the normalcy of the slave processors is monitored. On the other hand, the slave processor monitors the normalcy of the master processor. And in case some fault is detected, the fault announcement of the master processor is given to switch circuit EXCH. Thus circuit EXCH switches one of the slave processors to the master processor. As a result, both the reliability and the working efficiency can be increased for the system.

2. 发明专利

JPS5537680A DECENTRALIZED CONTROL SYSTEM 失效
公开(公告)号：JPS5537680A
公开(公告)日：1980-03-15
申请号：JP11100978
申请日：1978-09-08
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： SUGI KUNITOSHI , HORI YOSHINORI , OSANAI YOSHIHIRO , TOKITA YOSHIAKI , SEIKE KENJI
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To make decentralized control possible without providing a common memory, by storing a state control tape controlling a processing state in a memory in a processor. CONSTITUTION:Memory units which are arranged corresponding to processors and to and from which data can be written or read in the order of event occurrence are connected to common bus BS which transfers information between processors CP and NP. Since the memory in each processor is stored with state control tape TBL controlling a processing state, a next process is unconditionally determined and no process contradiction occurs. Therefore, the need for a common memory is eliminated and decentralized control can be attained.

3. 发明专利

JPS5537061A FAULT PROCESSING SYSTEM 失效
公开(公告)号：JPS5537061A
公开(公告)日：1980-03-14
申请号：JP11031578
申请日：1978-09-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： ENDOU KAZUMI , KAWASAKI TAKESHI , OSANAI YOSHIHIRO , OOYA TSUTOMU , TOKITA YOSHIAKI
IPC分类号： H04M3/22 , G06F15/16 , H04M3/08 , H04M3/24 , H04Q3/545
摘要： PURPOSE:To limit the effect of the fault for the multi-processor control exchange system by giving the fault processing through one of the central processors in case some fault occurs at the network control processor and performing the exchange process with other processors. CONSTITUTION:For instance, if some fault occurs at processor 2-1, the fault is informed to fault processor 3-0. And processor 3-0 sets up the blocking flag concerning processor 2-1 on the blocking flag holding register 14 at interface part 4. Thus the access to processor 2-1 is inhibited when the occupancy process is given for bus 6 in view of securing an access to processor 2-1 while the general exchange action is performed by central processor 3-j, 3-k and others. And the relation call process to processor 2-1 is held by queuing matrix buffer 15-j and others.

4. 发明专利

JPH0243630A INPUT CORRECTABLE EXPERT SYSTEM 失效
公开(公告)号：JPH0243630A
公开(公告)日：1990-02-14
申请号：JP19353688
申请日：1988-08-04
申请人： OKI ELECTRIC IND CO LTD
发明人： OHATA KEIJI , IKO SHINYA , OSANAI YOSHIHIRO
IPC分类号： G06F9/44
摘要： PURPOSE:To correct an input error with a simple operation by stacking input information and operating the contents of a work memory based on the information. CONSTITUTION:The title system includes a stack memory 1 having a storing position to accumulate the message of a question, the rule of the knowledge base or the storing position of a work memory 13 in respective steps and a storing position instructing means to instruct the position where the accumulation is executed at the newest out of the storing position of the stack memory 1. When an inference mechanism 3 receives an instruction from an input output means 10, the value of a storing position instructing means is returned up to the step related to the instruction, the contents of the step related to the instruction are read from the stack memory 1, the read contents are outputted to the input output means and the contents of the storing position of the work memory 13 corresponding to the sequence in which the storing position instructing means instructs are erased. Thus, with a simple operation, the input can be corrected.

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