专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS60117840A OUTPUT LEVEL ADJUSTING SYSTEM 失效
公开(公告)号：JPS60117840A
公开(公告)日：1985-06-25
申请号：JP22505583
申请日：1983-11-29
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SOEJIMA TETSUO , AMAMIYA SHIGEO , MURANO KAZUO , HAYASHI KAZUHIRO , INOUE TOMOJI
IPC分类号： H04B3/04 , H04L12/40
摘要： PURPOSE:To increase sufficiently a network termination and a terminal device by adjusting an output level from each terminal device so as to be a prescribed amplitude at a network termination reception point. CONSTITUTION:''0'' is inserted to a monitor pattern inserting position MT of Fig. (B) at first in a terminal device desired to be adjusted and the result is transmitted to an outgoing line T. The network terminal 1 receives it and reflects it as an MR to an outgoing line R. Then an output level adjusting device 8 of the terminal device increases the level by a minute level DELTAV and transmits the result to the line T. The network termination reflects it similarly as above. The operation like this is repeated and the output level incremented numbr of times is checked until the MR on the line R at the terminal device reaches ''1'' at first. Suppose that this is K-time, then the said incremental number of times as the output level of the final ''1'' code becomes an amplitude equivalent to 2K-times. The ''1'' code output level is adjusted so as to be received as the amplitude double the threshold value of the receiver of the network terminal from the terminal device independently of the range from the network termination of the terminal device.

2. 发明专利

JPS6041342A CLOCK SELECTION CONTROL SYSTEM 失效
公开(公告)号：JPS6041342A
公开(公告)日：1985-03-05
申请号：JP14923583
申请日：1983-08-17
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SOEJIMA TETSUO , AMAMIYA SHIGEO , MURANO KAZUO , OKUMURA YASUYUKI , INOUE TOMOJI
IPC分类号： H04L29/08 , H04L7/02 , H04L12/40
摘要： PURPOSE:To discriminate automatically the connection mode of a terminal equipment by discriminating whether the distance from a network terminating equipment to the nearest terminal equipment is shorter than a prescribed value or not, and outputting a clock signal of a fixed phase output or a digital phase synchronizing circuit output in accordance with this discriminated result. CONSTITUTION:The shortest terminal distance identifying circuit LID detects violation of a frame synchronizing signal to identify the distance from the network terminating equipment to the nearest terminal equipment on a basis of a frame phase pulse indicating the phase of the transmission frame synchronizing signal. If this distance is shorter than the prescribed value, a clock signal of a fixed phase is selected from a transmission control circuit SC by a selector SEL and is sent to a retiming circuit RTM. If said distance is identified that it is not shorter than the prescribed value, the output clock signal of a digital phase synchronizing circuit DPLL is selected by the selector SEL and is sent to the circuit RTM.

3. 发明专利

JPS6038947A COMMUNICATION SYSTEM 失效
公开(公告)号：JPS6038947A
公开(公告)日：1985-02-28
申请号：JP14695583
申请日：1983-08-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SOEJIMA TETSUO , AMAMIYA SHIGEO , MURANO KAZUO , HAYASHI KAZUHIRO , INOUE TOMOJI
IPC分类号： H04L12/00 , H04L11/00
摘要： PURPOSE:To ensure a spare bit by converting a data into an m-bit code so as to perform a survival control without contradiction at each n-bit (n

4. 发明专利

JPS6010833A FRAME PATTERN DETECTING CIRCUIT 失效
公开(公告)号：JPS6010833A
公开(公告)日：1985-01-21
申请号：JP11691683
申请日：1983-06-30
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： OKUMURA YASUYUKI , SOEJIMA TETSUO , WATANABE TOSHIAKI
IPC分类号： H04L25/49 , H04L7/00 , H04L7/04 , H04L7/08
摘要： PURPOSE:To prevent a pseudo pattern detecting pulse from being generated by inhibiting an output of a detecting circuit for a prescribed time after the generation of a true frame pattern detecting pulse in a transmission system using a Manchester code. CONSTITUTION:A monostable multivibrator 13 generates a pulse for a prescribed time (t) when the multivibrator 13 receives a differentiating pulse of a differentiating circuit 12 in a frame pattern detecting circuit where a different 2TS violation code having consecutive codes is used as a frame synchronism pattern. An output pulse of the monostable multivibrator 13 is applied as an inhibiting input of an inhibiting gate 14 so as to inhibit an output pulse of a flip-flop 11. Thus, the pseudo pattern detecting pulse is blocked and only the true frame pattern detecting pulse is outputted.

5. 发明专利

JPH0557786B2 失效
公开(公告)号：JPH0557786B2
公开(公告)日：1993-08-24
申请号：JP14923583
申请日：1983-08-17
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SOEJIMA TETSUO , AMAMYA SHIGEO , MURANO KAZUO , OKUMURA YASUYUKI , INOE TOMOJI
IPC分类号： H04L29/08 , H04L7/02 , H04L12/40

6. 发明专利

JPS6427332A MODULATION FORM CONVERTER 失效
公开(公告)号：JPS6427332A
公开(公告)日：1989-01-30
申请号：JP16926188
申请日：1988-07-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： AMANO FUMIO , MURANO KAZUO , SOEJIMA TETSUO , AOYAMA TOMONORI , YOSHIMURA HIROSHI , WAKABAYASHI KIYOHISA
IPC分类号： H04J1/00 , H04J3/00
摘要： PURPOSE:To reduce the quantity of noise equivalent to an output point by using a filter group as a noncirculation type polyphase filter (FIR filter)group with less noise production and a discrete filter conversion circuit (DFT) in combination. CONSTITUTION:A digital FDM signal is given to a thinning circuit 8-2 from an input terminal 8-1, and sent to a CDF filter (circulation type complex filter) 8-5 via a PDF/FIR filter group (noncirculation type polyphase filter group) 8-3, a 14-point DFT (discrete Fourier transformation circuit) 8-4 and the real part is extracted by a circuit Re(.)8-6. Then a TDM signal is extracted from an output terminal 8-9 via a waveform shaping circuit (BDF) 8-7 and a multiplexer circuit (MUX) 8-8. Since the PDF/FIR filter group is used in this way, the noise by the PDF/FIR 83 is less. Thus, noise from the FDM-TDM converter is reduced. Thus, the length of arithmetic operation word is less and the hardware is saved.

7. 发明专利

JPS6025344A BUS LINE PHASE SYNCHRONISM SYSTEM 失效
公开(公告)号：JPS6025344A
公开(公告)日：1985-02-08
申请号：JP13317883
申请日：1983-07-21
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SOEJIMA TETSUO , AMAMIYA SHIGEO , OKUMURA YASUYUKI
IPC分类号： H04L7/00 , H04L12/40
摘要： PURPOSE:To prolong the distance between a subscriber line terminator and a terminal device by transmitting a guard bit and a fixed bit from each terminal device ahead an information signal, and allowing the subscriber line terminator to detect a changing point from the guard bit to the fixed bit. CONSTITUTION:The guard bit G representing no signal state and the succeeding fixed bit thereto having a prescribed code ahead the information signal are transmitted when the information signal is transmitted onto an incoming line frame from each terminal device in the information transmission system where the subscriber line terminator and many terminal devices are connected by a bus transmitting a bi-phase code. In detecting the changing point from the no signal state to the fixed bit on the incoming line frame, the subscriber line terminator generates a gate signal having a time width passing the information signal of the channel and regenerates the extracted information by using the clock of the same phase as the outgoing line frame.

8. 发明专利

JPS5797246A TDM-FDM CONVERTER 失效
公开(公告)号：JPS5797246A
公开(公告)日：1982-06-16
申请号：JP17360480
申请日：1980-12-09
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： AMANO FUMIO , MURANO KAZUO , SOEJIMA TETSUO , AOYAMA TOMONORI , YOSHIMURA HIROSHI , WAKABAYASHI KIYOHISA
IPC分类号： H04J1/05 , H04J1/00 , H04J3/00 , H04J4/00
摘要： PURPOSE:To directly make TDM-FDM conversion and to simplify the constitution of a converter, by reducing the amount of operation together with an FIR filter and a modulation section. CONSTITUTION:An inputted 1 TDM multiplex signal is separated at 2 and a signal corresponding to each channel CH is inputted to a multiplying circuit 3. An odd channel CH is shifted by -2kHz at circuits 6-1-6-11 through a cyclic type digital filter 4 in 8kHz operation and a noncyclic type digital FIR filter 5 of 16kHz operation, and an even channel is shifted by +2kHz at circuits 6-2- 6-12. Next, additions 7-1-7-6 are made, and through an FIR filter 8 of 32kHz operation, -4kHz shift is made at 9-1-9-5 circuit and +4kHz shift is made at 9-2- 9-6 circuits and additions 10-1-10-3 are made. Through FIR filters 11-1- 11-3 of 224kHz operation, a real part is picked up at filter 15 via multiplication circuits 12-1, 12-2 and an addition circuit 13, and a digital FDM signal is outputted at 16.

9. 发明专利

JPS56122545A TIME DIVISION MULTIPLEXXFREQUENCY DIVISION MULTIPLEX CONVERTOR 失效
公开(公告)号：JPS56122545A
公开(公告)日：1981-09-26
申请号：JP2633780
申请日：1980-03-03
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： AMANO FUMIO , MURANO KAZUO , SOEJIMA TETSUO , AOYAMA TOMONORI , YOSHIMURA HIROSHI , WAKABAYASHI KIYOHISA
IPC分类号： H04J1/05 , H04J1/00 , H04J3/00 , H04J4/00
摘要： PURPOSE:To reduce a noise amount converted at the output point by constituting a filter by combination of a discrete filter converting circuit and a noncyclic type polyphase filter group whose noise generating amount is a little, when a time division multiple signal is directly converted to a frequency division multiple signal at the multiple level. CONSTITUTION:A time division multiple signal TDM from the input terminal 1 is divided into each channel by the separating circuit DEMUX11, it is made an odd or even channel by the waveform shaping circuit BDF12, the even channel is phase- inverted by the multiplying circuit 13, and after that, each signal is provided to the cyclic type complex filter CDF14, and it is converted to a complex signal. This complex signal is provided to the discrete Fourier converting circuit 14 point DFT15, and it is converted to a complex digital signal by said DFT16 and the noncyclic type polyphase filter group (PDF-FIR filter group) 16. Moreover, the real number part is output by the RE [.] circuit 17, it is compounded by the compounding circuit 18, and a frequency division multiple signal FDM is output from the output terminal 10. And, a noise amount is reduced by combination of the filter group 16 and the filter 14.

10. 发明专利

JPS55118179A ARITHMETIC CIRCUIT 失效
公开(公告)号：JPS55118179A
公开(公告)日：1980-09-10
申请号：JP2432079
申请日：1979-03-02
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MURANO KAZUO , SOEJIMA TETSUO , AMANO FUMIO , WAKABAYASHI KIYOHISA
IPC分类号： G06F17/14 , G06F15/78
摘要： PURPOSE:To save the multiplier or the like which forms the arithmetic circuit for the arithmetic circuit for Radix 3 emerging when the high-speed Fourier conversion is carried out for the discrete signals, by giving the calculation to the signal flow in division into the real part and the imaginary part each. CONSTITUTION:The I which shows Radix 3 emerging when the high-speed Fourier conversion is given to the discrete signal is divided into the real part and the imaginary part each for calculation to feature Eq. II. In such arithmetic circuit, figures 11-18 are arithmetic circuits, and 19-22 are adder/subtractor circuits respectively. And 11/13/19, 12/14/20, 15/17/21 and 16/18/22 deliver signals E, F, G and H each after the fixed operation. At the same time, adder/subtractor circuits 23-26 deliver signals Q, R, S and T each after the operation. Furthermore, adder/subtractor circuits 33-38 perform the prescribed operation to deliver real and imaginary parts XR, XI, YR, YI, ZR and ZI of output signals X, Y and Z each. With this circuit, both the adders and subtractors can be saved more than the conventional calculation method.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式