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1. 发明专利

JP2001141784A SEMICONDUCTOR DEVICE TEST CIRCUIT 失效
公开(公告)号：JP2001141784A
公开(公告)日：2001-05-25
申请号：JP31937199
申请日：1999-11-10
申请人： FUJITSU LTD
发明人： SUGANO HIROAKI
IPC分类号： G06F11/22 , G01R31/28 , G01R31/30 , G01R31/3185
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device test circuit capable of adjusting the SCAN operation period by a simple means. SOLUTION: A period adjusting flip-flop is added to a rearmost stage in a SCAN circuit included in a system circuit configured in a semiconductor device (an LSI). Thereby, the SCAN operation period can be easily adjusted.

2. 发明专利

JPH11142477A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH11142477A
公开(公告)日：1999-05-28
申请号：JP30413797
申请日：1997-11-06
申请人： FUJITSU LTD
发明人： SUGANO HIROAKI
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G11C11/417 , G11C19/00 , H03K3/037
摘要： PROBLEM TO BE SOLVED: To select the optimum flip-flop(FF) and increase the reliability of a FF test by mixedly arranging a first shift register having multiple first FFs containing a first latch circuit and a second latch circuit and a second shift register having multiple second FFs containing a third latch circuit and a fourth latch circuit. SOLUTION: A first shift register 14 latches the scan signal SI1 synchronously with a first test clock CLKA and outputs the latched scan signal SL1 synchronously with a second test clock CLKB to take a shift action during a test. A second shift register 24 latches a scan signal SI2 synchronously with the rise of a second system clock SCK2 and outputs the latched scan signal SI1 synchronously with the fall of the second system clock SCK2 to take a shift action during the test. An FF is selected based on the clock skew of the register and a circuit scale.

3. 发明专利

JPH01233377A FUNCTION TEST 失效
公开(公告)号：JPH01233377A
公开(公告)日：1989-09-19
申请号：JP5933188
申请日：1988-03-15
申请人： FUJITSU LTD
发明人： SUGANO HIROAKI , MORI YUTAKA
IPC分类号： G01R31/317 , G01R31/28 , H01L21/66
摘要： PURPOSE:To reduce a test time with a greater test speed, by generating a test input pattern using an exclusive OR between a fixed value data output per specified cycle and a timing pulse having the same cycle as that of the data output and a width narrower than the data output. CONSTITUTION:In the generation of an input pattern, a test input pattern is generated using an exclusive OR between a data output taking a value binary and determined at each specified cycle and a timing pulse having the same cycle as, and a width narrower than, the data output. As the data output and the timing pulse are both binary and the width of the timing pulse is narrower than that of the data output, there is sure to be a part having the data output level coinciding with the timing pulse level and that having none within one cycle. Thus, two different DC levels can be generated within one cycle by obtaining an exclusive OR between the these parts, thereby enabling a reduction in the test time.

4. 发明专利

JPS57133710A CONSTRUCTION OF VARIABLE DELAY LINE 失效
公开(公告)号：JPS57133710A
公开(公告)日：1982-08-18
申请号：JP1946581
申请日：1981-02-12
申请人： FUJITSU LTD
发明人： SUGANO HIROAKI
IPC分类号： H03H7/30 , H03H7/32
摘要： PURPOSE:To achieve a delay line possible for timing adjustment, by a construction that zig zag pattern and straight pattern are in parallel provided via a dielectric substance layer on a conductor layer formed on an insulation substrate and a conductive brush is brought into contacted with both the patterns. CONSTITUTION:A ground pattern 3 consisting of conductor film is formed on the surface of an isolation substrate 2. A zig zag pattern 5 and a stright pattern 6 are formed on this ground pattern 3 via a dielectric substance layer 4. Further, on four corners, an input round 51 connected to the pattern 5 and a pair of ground rounds 31 introduced from a fixed output round 52 and the pattern 3 are formed. A variable output round 61 is formed from the center of the straight pattern 6 to the side. An elastic sliding brush 7 pressing and sliding with each pattern is provided by bridging the patterns 5 and 6. The timing adjustment of delay time of a delay line can be made by minute feeding of a mechanism 8.

5. 发明专利

JP2007072961A Database retrieval method, program, and system 审中-公开
标题翻译：数据库检索方法，程序和系统
公开(公告)号：JP2007072961A
公开(公告)日：2007-03-22
申请号：JP2005262033
申请日：2005-09-09
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KOYAMA YOSHIE , SUGANO HIROAKI
IPC分类号： G06F17/30
CPC分类号： G06F17/30595 , Y10S715/968
摘要： PROBLEM TO BE SOLVED: To perform efficient retrieval work in which retrieval results can automatically be obtained across a plurality of steps with one retrieval operation without needing operation of re-retrieval for each entry to be retrieved further during retrieval. SOLUTION: A retrieval condition designation part 22 designates a retrieval condition entry and designates a re-retrieval condition entry to be re-retrieved on the basis of the retrieval results according to the retrieval designation condition. A retrieval processing part 24 extracts an entry value corresponding to the re-retrieval condition entry from the retrieval result of a database 16 by the retrieval condition entry and repeats retrieval of the database 16 with the entry value as the retrieval condition entry until no entry value is extracted. A retrieval result display part 26 displays the retrieval result by the retrieval processing part 24 as a list. In the list display of the retrieval result, all entries all rows writing together display is performed in which all the entries of each retrieval result by a plurality of steps retrieval are arranged in a row direction and each retrieval result is arranged in a column direction in order of retrieval or all entries one row writing together display is performed in which all the entries of each retrieval result by the plurality of steps retrieval are arranged in a row direction in order of retrieval. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：执行有效的检索工作，其中可以通过一个检索操作在多个步骤中自动获得检索结果，而不需要在检索期间进一步检索的每个条目的重新检索操作。解决方案：检索条件指定部分22指定检索条件条目，并根据检索指定条件，根据检索结果指定要重新检索的重新检索条件条目。检索处理部分24通过检索条件条目从数据库16的检索结果中提取与重新检索条目条目相对应的条目值，并重复以条目值作为检索条件条目的数据库16的检索，直到没有条目值被提取。检索结果显示部26将检索处理部24的检索结果作为列表显示。在检索结果的列表显示中，执行所有行一起写入显示的所有条目，其中通过多个步骤检索的每个检索结果的所有条目被排列在行方向上，并且每个检索结果以列方向排列执行检索顺序或一行一起写入显示的所有条目，其中通过多个步骤检索的每个检索结果的所有条目以检索的顺序排列在行方向。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JPS58142520A METHOD OF PRODUCING CONDENSER 失效
公开(公告)号：JPS58142520A
公开(公告)日：1983-08-24
申请号：JP2577782
申请日：1982-02-19
申请人： FUJITSU LTD
发明人： SUGANO HIROAKI
IPC分类号： H01G4/255

7. 发明专利

JPS55102293A METHOD OF FIXING COMPONENT 失效
公开(公告)号：JPS55102293A
公开(公告)日：1980-08-05
申请号：JP1003479
申请日：1979-01-31
申请人： FUJITSU LTD
发明人： TANAKA KATSUO , SUGANO HIROAKI , SHIROTSUKI TSUNEO
IPC分类号： F16B13/00 , H05K1/18

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