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1. 发明专利

JP2006209797A Cache coherence device 有权
标题翻译：高速缓存设备
公开(公告)号：JP2006209797A
公开(公告)日：2006-08-10
申请号：JP2006077052
申请日：2006-03-20
申请人： Fujitsu Ltd , Pfu Ltd , 富士通株式会社 , 株式会社Pfu
发明人： KABEMOTO AKIRA , SHIBATA NAOHIRO , MUTA TOSHIYUKI , SHIMAMURA TAKAYUKI , SUGAWARA HIROHIDE , NISHIOKA JUNJI , SASAKI TAKASATO , SHINOHARA SATOSHI , NAKAYAMA YOUZOU , SAKURAI JUN , ISHIHATA HIROAKI , HORIE KENJI , SHIMIZU TOSHIYUKI
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F2212/1016
摘要： PROBLEM TO BE SOLVED: To improve processing performance by arbitrating competition between caches of a plurality of processors incorporated in a plurality of processor modules and local storage divisionally disposed in the main storage of each the module to efficiently obtain cache coherence. SOLUTION: When access from a certain processor 16 in the module and access from an external processor module 10-2 are competed to a cache unit 18 of the processor module 10-2 and when the processor 16 precedingly acquires the cache unit 18, the processor 16 makes a processor module 10-1 perform an instruction of a retrial, stores the competed processor module 10-1 and an access address, instructs the retrial when receiving an access command for the processor module except the competed processor module 10-1 after the access completion of the processor 16 itself, and preferentially receives the access command by the retrial of the competed second processor module 10-1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过仲裁在多个处理器模块中并入的多个处理器的高速缓存之间的竞争以及分开设置在每个模块的主存储器中的本地存储器之间的竞争来提高处理性能，以有效地获得高速缓存一致性。解决方案：当来自模块中的某个处理器16的访问和来自外部处理器模块10-2的访问与竞争者到处理器模块10-2的高速缓存单元18，并且当处理器16之前获取高速缓存单元18 处理器16使得处理器模块10-1执行重试指令，存储竞争的处理器模块10-1和访问地址，在接收除了竞争的处理器模块10之外的处理器模块的访问命令时指示重试 1处理器16本身的访问完成之后，并且优先地通过竞争的第二处理器模块10-1的重试来接收访问命令。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006179034A Cache coherence system 有权
标题翻译：高速缓存系统
公开(公告)号：JP2006179034A
公开(公告)日：2006-07-06
申请号：JP2006077475
申请日：2006-03-20
申请人： Fujitsu Ltd , Pfu Ltd , 富士通株式会社 , 株式会社Pfu
发明人： KABEMOTO AKIRA , SHIBATA NAOHIRO , MUTA TOSHIYUKI , SHIMAMURA TAKAYUKI , SUGAWARA HIROHIDE , NISHIOKA JUNJI , SASAKI TAKASATO , SHINOHARA SATOSHI , NAKAYAMA YOUZOU , SAKURAI JUN , ISHIHATA HIROAKI , HORIE KENJI , SHIMIZU TOSHIYUKI
IPC分类号： G06F12/08
摘要： PROBLEM TO BE SOLVED: To realize high speed cache coherence by separating the bus operation of cache coherence in a processor module from the bus operation of the cache coherence between processor modules by common bus configurations with two hierarchies. SOLUTION: In addition to a directory storage part 30 of a memory management unit 26, a bus connecting unit 32 is provided with a second directory storage part. A stand-by status due to an access request to the other processor module is registered by cache line units in the second directory storage part, and when the access of the same cache line is recognized by referring to the storage part of the second directory in response to access from the other processor module, a busy reply is made. Thus, it is not necessary to transmit any access request of the other processor module to the memory management unit 26 side, and it is possible to quicken the busy reply. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过将处理器模块中的高速缓存一致性的总线操作与通过具有两个层次的公共总线配置的处理器模块之间的高速缓存一致性的总线操作分离来实现高速缓存一致性。
解决方案：除了存储器管理单元26的目录存储部分30之外，总线连接单元32还设置有第二目录存储部分。由于对另一个处理器模块的访问请求的备用状态由第二目录存储部分中的高速缓存行单元注册，并且当通过参考第二目录的存储部分来识别相同的高速缓存行的访问时响应来自另一个处理器模块的访问，进行了忙碌的回复。因此，不需要将其他处理器模块的任何访问请求发送到存储器管理单元26侧，并且可以加快忙碌的应答。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005216317A Queue device 有权
标题翻译： QUEUE DEVICE
公开(公告)号：JP2005216317A
公开(公告)日：2005-08-11
申请号：JP2005029027
申请日：2005-02-04
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIRAKI NAGATAKE , KOYANAGI YOICHI , HORIE KENJI , SHIMIZU TOSHIYUKI , ISHIHATA HIROAKI
IPC分类号： G06F13/12 , G06F5/06 , G06F13/36 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide a queue device in which a data writing device can get ready to output data to a queue without waiting until the queue makes an "available space" even when the queue comes full. SOLUTION: The queue device includes a FIFO buffer 41 into which a plurality of processes write packets, a memory means 42, a data saving means 43 and a data restoring means 44. The data saving means 43 takes incomplete packet data written during a process A to save them into the memory means 42 out of the FIFO buffer 41, upon switching of an execution right from a process A to another process B while the process A writes a packet into the FIFO buffer 41. The data restoring means 44, upon transferring of the execution right to the process A again, transfers the packet data saved in the memory means 42 to the FIFO buffer before the process A starts executing. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种队列装置，其中数据写入装置可以准备好将数据输出到队列，而不等待直到队列成为“可用空间”，即使队列满了。解决方案：队列设备包括多个进程写入分组的FIFO缓冲器41，存储装置42，数据保存装置43和数据恢复装置44.数据保存装置43获取在当处理A将分组写入FIFO缓冲器41时，将处理A的执行权切换到另一个进程B，将进程A保存到FIFO缓冲器41中的存储装置42中。数据恢复装置44 在再次将执行权转移到处理A之后，在处理A开始执行之前将保存在存储装置42中的分组数据传送到FIFO缓冲器。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JPH06223044A METHOD AND DEVICE FOR MESSAGE COMMUNICATION OF PARALLEL COMPUTER 失效
公开(公告)号：JPH06223044A
公开(公告)日：1994-08-12
申请号：JP960893
申请日：1993-01-25
申请人： FUJITSU LTD
发明人： SHIMIZU TOSHIYUKI , ISHIHATA HIROAKI
IPC分类号： G06F15/16 , G06F15/177 , G06F15/80
摘要： PURPOSE:To reduce the communication of a master processor(PE) and eliminate the convergence of a load on the master processor(PE) when a new task is executed. CONSTITUTION:The parallel computer is constituted by connecting plural computers each consisting of a network device(ND) 1 equipped with an arbiter(ABT) 12 which refers to the header parts (1)a of input messages (1) from plural directions and Judges destinations in other plural directions and a processor element(PE) 2; and a processor element(PE) 2 is provided with a monitor(Mon) 20 monitoring the state of the load on its processor(PE) 2, the amount and length of messages already received, the time of the presence of a message (1) in the network from its transmission, a transmission destination specified on the transmission side of the message (1), etc., and its output is sent to the arbiter(ABT) 12, which routes the received message (1) on the basis of the header part (1) a of the message (1) and information from the monitor(Mon).

5. 发明专利

JPH0668019A DMA CONTROLLER 失效
公开(公告)号：JPH0668019A
公开(公告)日：1994-03-11
申请号：JP22282492
申请日：1992-08-21
申请人： FUJITSU LTD
发明人： SHIMIZU TOSHIYUKI , ISHIHATA HIROAKI
IPC分类号： G06F13/28 , G06F13/38
摘要： PURPOSE:To provide the DMA controller which increases the DMA start speed by simplifying data setting at the time of DMA start. CONSTITUTION:This DMA controller consists of a decoder DEC which decodes an upper address signal (a) to be the DMA start instruction of the address signal from a central processing unit CPU, a register MADDR where a middle address signal of the address signal (a) from the central processing unit CPU is held as the start address for access to a memory MEM, a register CNT where the lower address signal of the address signal (a) from the central processing unit CPU is held as the counted value of data transferred by DMA transfer, and a sequencer SEQ which starts DMA to control the data transfer of DMA when the result of decoding of the decoder DEC indicates that a DMA start command is designated.

6. 发明专利

JPH04218853A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH04218853A
公开(公告)日：1992-08-10
申请号：JP7330391
申请日：1991-04-05
申请人： FUJITSU LTD
发明人： SHIMIZU TOSHIYUKI , HORIE KENJI
IPC分类号： G06F13/28
摘要： PURPOSE:To efficiently perform data transfer from an input device to memory and from the memory to an output device without satisfying two conditions that address alignment is arranged and that the total amount of transfer data is set at a value, for example, the multiple of four words. CONSTITUTION:The amount of data in the buffet 12 of the input device 13 is informed to a memory write control means 14, and the memory write control means 14 decides the transfer size of the data from the input device 13 to the memory 9 by checking the address alignment of the memory 9. Also. a memory readout means 18 recognizes the number of free areas in the buffer 16 of the output device 17, and decides the transfer size of the data from the memory 10 to the output device 17 by checking the address alignment of the memory 10.

7. 发明专利

JPH0469760A DATA COLLECTION CONTROL SYSTEM FOR PARALLEL COMPUTER 失效
公开(公告)号：JPH0469760A
公开(公告)日：1992-03-04
申请号：JP18207390
申请日：1990-07-10
申请人： FUJITSU LTD
发明人： KATO SADAYUKI , ISHIHATA HIROAKI , HORIE KENJI , INANO SATOSHI , SHIMIZU TOSHIYUKI
IPC分类号： G06F15/173 , G06F13/38 , G06F15/16
摘要： PURPOSE:To collect the data distributed to plural processors at a high speed by providing a transfer control circuit for determining an output sequence of data on each processor, monitoring the number of transfers of data on a common bus by a transfer control circuit and controlling to send out data which each processor has. CONSTITUTION:Processors P1, ... for sending data are provided with transfer control circuits U1, U2, ... for determining an output sequence of the data, respectively. Each transfer control circuit U1, U2, ... allows the data transfer to wait until it can execute the data transfer, while monitoring the number of data transfers on a common bus L in accordance with a transfer schedule of the data set in advance. Also, on each processor P1, ..., transmitting buffers F1, ... of FIFO for preparing data to be transmitted in advance are provided, and the transfer is executed without the time of arbitration between the processors. In such a way, the data collection can be executed at a high speed.

8. 发明专利

JPH03150659A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH03150659A
公开(公告)日：1991-06-27
申请号：JP29068489
申请日：1989-11-08
申请人： FUJITSU LTD
发明人： SHIMIZU TOSHIYUKI , ISHIHATA HIROAKI
IPC分类号： G06F12/08 , G06F15/16 , G06F15/173
摘要： PURPOSE:To lighten overhead to be caused at the time of starting message transfer by providing a means to transfer directly a message from a cache memory to a device through the same operation as to flash cached data to a main storage device. CONSTITUTION:A cache controller 14 (15) is provided with a mechanism which provides a processor element (PE) 1 with a specified data transfer instruction, and in addition, detects (epsilon) that the data can be transferred to a port 13, and executes the specified data transfer instruction. The data existing on a cache memory 11(main storage device 12) is transferred from the cache memory 11(main storage device 12) directly to the port 13 by the specified data transfer instruction. The data not cached on the cache memory 11 is transferred from the main storage device (MM) 12 to the port 13. Thus, a small message (data) between the processor elements (PE) can be transferred efficiently, and the overhead can be lightened.

9. 发明专利

JPS62107392A CASH DISPENSER 失效
公开(公告)号：JPS62107392A
公开(公告)日：1987-05-18
申请号：JP24826185
申请日：1985-11-06
申请人： FUJITSU LTD
发明人： SHIMIZU TOSHIYUKI
IPC分类号： G06M7/06 , G07D9/00
摘要： PURPOSE:To count the number of remaining sheets after a near end is detected, by feeding and counting the paper money from a safe, when the near end is detected, bringing it to a reflux to its safe again, and also counting the number of sheets of received and paid money, by a sheet number counter. CONSTITUTION:By the detection of a near end detecting part 11, a feed processing part 13 feeds paper money from a safe, also counts the number of sheets of this paper money, and brings it to the reflux to the safe. A sheet number counter 14 counts the number of counted sheets and the number of sheets by received and paid money, and counts the number of remaining sheets in the safe. The number of remaining sheets after the near end is detected can be counted in a short time. Paper money in the safe can be effectively paid by setting newly a value which subtracts the number of sheets of paid money from the value of a limit sheet number register 15, and adds the number of sheets of received money, to the limit sheet number register.

10. 发明专利

JPS61216083A AUTOMATIC TICKET ISSUING DEVICE 失效
公开(公告)号：JPS61216083A
公开(公告)日：1986-09-25
申请号：JP2782185
申请日：1985-02-15
申请人： FUJITSU LTD
发明人： YONEDA MASAYOSHI , TOKURA KATSUYUKI , SHIMIZU TOSHIYUKI
IPC分类号： G06Q30/06 , G06Q50/00
摘要： PURPOSE:To simplify operation by storing reservation information, guiding a purchaser of the changeover to purchase by a cash when receiving a non-permission for issuing a ticket by a dealing card to extract the reservation information and carrying out the ticket issuing processing by a cash. CONSTITUTION:When a reserved seat ticket is purchased by a credit card, is an user inputs the credit card, this information if read, and the card information is transmitted to a central device 1. From the central device 1. the reserved information (destination, flight number, kind of ticket or the like) is transmitted, in accordance with a recognition response (request for issuing a ticket), a permission of issuing the ticket is obtained, the ticket issuing is performed, and the central unit 1 performs a pull down processing of said card. When the non-permission for issuing the ticket by said card is received from the central unit 1 during the ticket issuing processing by the card, a card ticket issuing and processing section 13 informs to a selecting/change-over section and displays cash change-over guide on a display section 9. A cash ticket issuing processing section 17 receiving the change-over processing extracts a stored reserved information from a card reserved information memory section 18 to obtain the recognition of the contents and continues to process the cash ticket issuing thereafter.

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