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1. 发明专利

JPS6110352A Subscriber line interface circuit 失效
标题翻译：订户线接口电路
公开(公告)号：JPS6110352A
公开(公告)日：1986-01-17
申请号：JP12997884
申请日：1984-06-26
申请人： Fujitsu Ltd
发明人： FUNAKI TETSUJI , KOIKE JIYUNICHI , WARABINE KAZUYUKI , IITAKA EIJI , HIBINO OSAMU
IPC分类号： H04M3/06 , H04M19/02
CPC分类号： H04M19/023
摘要： PURPOSE:To miniaturize a call signal transmission circuit by using a switching regulator for a call signal transmission circuit to generate a low frequency call signal in 16Hz without using a low frequency transformer. CONSTITUTION:The call signal generator circuit CRG consists of a high frequency transformer HFT, a switching circuit SWC, a rectifier circuit REF and a counter CNT. A ring-on signal RG from a sub-controller and a switching regulator high frequency signal from the counter CNT are inputted to the switching circuit SWC. The switching circuit SWC ANDs the signals, drives a transistor (TR) and its output is fed to the primary winding of the high frequency transformer HFT. Thus, a signal boosted to 75V, 16Hz required for the ringing of a bell is obtained at the secondary winding of the transformer from a voltage 24V at the primary winding and the boosted signal is rectified by the rectifier circuit REF and a continuous ringer signal tone is obtained.
摘要翻译：目的：通过使用呼叫信号传输电路的开关稳压器，在不使用低频变压器的情况下，以16Hz生成低频呼叫信号，来使呼叫信号传输电路小型化。构成：呼叫信号发生器电路CRG包括高频变压器HFT，开关电路SWC，整流电路REF和反向CNT。来自子控制器的接通信号RG和来自计数器CNT的开关调节器高频信号被输入到开关电路SWC。开关电路SWC对信号进行驱动，驱动晶体管（TR），其输出被馈送到高频变压器HFT的初级绕组。因此，在变压器的次级绕组从初级绕组的电压24V获得提升到75V，16Hz所需的信号，并且升压信号由整流电路REF和连续的振铃信号音获得。

2. 发明专利

JPS5784653A DIAL PULSE CONVERSION SYSTEM 失效
公开(公告)号：JPS5784653A
公开(公告)日：1982-05-27
申请号：JP16027080
申请日：1980-11-14
申请人： FUJITSU LTD
发明人： SUZUKI KATSUO , KOIKE JIYUNICHI , WARABINE KAZUYUKI
IPC分类号： H04M11/00 , H04M1/26 , H04M1/50 , H04M1/677
摘要： PURPOSE:To enable to install a push button PB dial conversion circuit to a rotating dial type telephone set, by keeping an output for a prescribed time on an output line of a gate circuit corresponding to the number of dials, when a series of dial pulse is finished. CONSTITUTION:The off-hooking of a telephone set Tel is detected with a photo coupler PC, and a JK flip-flop FF1. When dialing is made at a telephone set Tel, one-shot multivibrator MM1 is started with the 1st dial pulse, and an output is made for a prescribed time covering a series of dial pulse and the off- hooking of the telephone set Tel is displayed. The number of interruption of a dial is counted with a count circuit COUNT via a one-shot multivibrator MM3, the result is decoded at a decoder DEC and outputted on output lines l1-l10 of a gate circuit G coresponding to the number of dials.

3. 发明专利

JPS5617097A METHOD OF MANUFACTURING PRINTED BOARD 失效
公开(公告)号：JPS5617097A
公开(公告)日：1981-02-18
申请号：JP9253579
申请日：1979-07-23
申请人： FUJITSU LTD
发明人： KOIKE JIYUNICHI , TSUCHIYA AKIRA
IPC分类号： H05K3/00 , H01L21/82 , H05K1/02 , H05K3/02

4. 发明专利

JPS5552287A METHOD OF MANUFACTURING PRINTED BOARD 失效
公开(公告)号：JPS5552287A
公开(公告)日：1980-04-16
申请号：JP12512978
申请日：1978-10-13
申请人： FUJITSU LTD
发明人： AEBA KEIJI , TSUCHIYA AKIRA , GOTOU TSUNEYASU , KOIKE JIYUNICHI
IPC分类号： H05K3/20

5. 发明专利

JPS5527688A METHOD OF FORMING PRINTED BOARD CIRCUIT PATTERN 失效
公开(公告)号：JPS5527688A
公开(公告)日：1980-02-27
申请号：JP10157778
申请日：1978-08-21
申请人： FUJITSU LTD
发明人： AEBA KEIJI , TSUCHIYA AKIRA , KANAI TADASHI , GOTOU TSUNEYASU , KOIKE JIYUNICHI
IPC分类号： H05K3/18

6. 发明专利

JPS5383080A METHOD OF PRODUCING PRINTED BOARD 失效
公开(公告)号：JPS5383080A
公开(公告)日：1978-07-22
申请号：JP15748376
申请日：1976-12-28
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TSUCHIYA AKIRA , KOIKE JIYUNICHI , AEBA KEIJI , ONOSE KATSUHIDE
IPC分类号： H05K3/42 , H05K3/00 , H05K3/18

7. 发明专利

JPS58207785A DISCRIMINATING SYSTEM OF REPETITIVE PERIOD 失效
公开(公告)号：JPS58207785A
公开(公告)日：1983-12-03
申请号：JP9070782
申请日：1982-05-28
申请人： FUJITSU LTD , HASEGAWA DENKI SEISAKUSHO
发明人： YAMAUCHI MASAAKI , KOIKE JIYUNICHI , SUZUKI KATSUO , WARABINE KAZUYUKI , MAEHARA TAKASHI
IPC分类号： H04M3/60 , H04Q1/32 , H04Q3/58
摘要： PURPOSE:To discriminate the incoming period of a short pulse train, by providing the 1st and the 2nd monostable multivibrators having a set time being intermediate period between two kinds of repetitive periods. CONSTITUTION:A lighting signal transmitted in parallel with a lamp 4 corresponding to a main wire from a display processing circuit is differentiated, a positive half wave only is extracted and transmitted to the monostable multivibrators MV1, MV2 via gates G1, G2. A set time tau1 of the monostable multivibrator MV1 and a set time tau2 of the monostable multivibrators MV3, MV2 are set with signal repetitive periods T1, T2 so as to satisfy the conditions as tau1

8. 发明专利

JPS5775368A Connection system of multiprocessor 失效
标题翻译：多处理器连接系统
公开(公告)号：JPS5775368A
公开(公告)日：1982-05-11
申请号：JP15178280
申请日：1980-10-29
申请人： Fujitsu Ltd
发明人： SUZUKI KATSUO , KOIKE JIYUNICHI , WARABINE KAZUYUKI
IPC分类号： G06F15/167
CPC分类号： G06F15/167
摘要： PURPOSE:To ensure the assured transfer of data and at the same time to reduce the time of process as well as to increase the process capacity, by carring out the transfer of data between a master processor and each subprocessor with the clock signal in good order nad with highefficiency. CONSTITUTION:The clock signal CL which is turned to 1 and 0 in the 1st and 2nd periods respectively is applied to a master processor MPU in the form of an interruption signal IRQ. At the same time, gates MG1 and MG2 are opened. While 1 of the signal CL is inverted by an inverter INV to O. Thus no interruption IRQ is carried out to a subprocessor SPU#O, and tages SG1 and SG2 are closed. And an acceess is inhibited to a radom memory RAM from subprocessors SPUs#O-#n via a sub-bus SB. Then the master processor MPU gives an access to the memory RAM via a main bus MB plus the gates MG1 and MG2. When the signal CL is set at O, the gates MG1 and MG2 are closed with the gates SG1 and SG2 opened. And the processor SPU#O receives an interruption IRQ.
摘要翻译：目的：为了确保数据的有效传输，同时减少处理时间以及增加处理能力，通过在主处理器和每个子处理器之间传输数据，时钟信号顺序良好没有高效率。构成：分别在第1和第2周期中变为1和0的时钟信号CL以中断信号IRQ的形式施加到主处理器MPU。同时，门MG1和MG2打开。当信号CL的1由反相器INV反相时，因此不对中间件SPU＃O执行中断IRQ，并且计数器SG1和SG2闭合。并且通过子总线SB，从子处理器SPU＃O-＃n禁止对雷达存储器RAM的访问。然后，主处理器MPU通过主总线MB加上门MG1和MG2来访问存储器RAM。当信号CL设置为O时，门MG1和SG2被打开，门MG1和MG2闭合。并且处理器SPU＃O接收中断IRQ。

9. 发明专利

JPS5552297A METHOD OF MANUFACTURING METALLIC CORE MULTILAYER PRINTED BOARD 失效
公开(公告)号：JPS5552297A
公开(公告)日：1980-04-16
申请号：JP12513178
申请日：1978-10-13
申请人： FUJITSU LTD
发明人： AEBA KEIJI , TSUCHIYA AKIRA , GOTOU TSUNEYASU , KOIKE JIYUNICHI
IPC分类号： H05K3/44 , H05K3/46

10. 发明专利

JPS5539673A METALLIC CORE INSERTED PRINTED BOARD 失效
公开(公告)号：JPS5539673A
公开(公告)日：1980-03-19
申请号：JP11330778
申请日：1978-09-14
申请人： FUJITSU LTD
发明人： AEBA KEIJI , TSUCHIYA AKIRA , KANAI TADASHI , GOTOU TSUNEYASU , KOIKE JIYUNICHI
IPC分类号： H05K1/05 , H05K3/44

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