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    • 2. 发明专利
    • DELAY CIRCUIT STRUCTURE
    • JPH0239604A
    • 1990-02-08
    • JP18814688
    • 1988-07-29
    • FUJITSU LTD
    • SATO NORIOOKAMURA HAJIMEISHIZAKA TAEKO
    • H05K1/14H01P9/02H05K1/02H05K3/46
    • PURPOSE:To miniaturize the title delay circuit structure and to densify the structure by adhering two insulating substrates to each other so that respective ground patterns on the rears of the two insulating substrates can join with each other and mutually connecting the strip lines of both the two substrates through through holes provided for positions to avoid the ground patterns so as to penetrate both the two substrates. CONSTITUTION:Ground patterns 12 and 22 of substrates 10 and 20 are opposed to each other, further the substrates 10 and 20 are solder-joined and adhered to each other so that through holes 31 and 41 of both the substrates 10 and 20 can coincide with each other and unified, and at the same time, the through holes 31 and 41 are also joined with each other with internal solder 50. Since a longitudinal directional dimension l' of the second substrate 20 is smaller than a longitudinal directional dimension l of the first substrate 10 (l>l') here, the lower area of the first substrate 10 never overlaps with the second substrate 20. Consequently, two ground terminals 16 are linked to both the lower edges of the first substrate 10, which never overlaps with the second substrate 20, by caulking or soldering, etc. In the same manner, signal leads 14a and 14b are linked to conductor land parts 13 and 23 at the outer edges of spiral strip lines 11 and 21 of both the substrates 10 and 20 by caulking or soldering, etc. Thus, the structure can be miniaturized and densified.
    • 5. 发明专利
    • Collision testing device
    • 碰撞测试设备
    • JP2006275676A
    • 2006-10-12
    • JP2005093492
    • 2005-03-29
    • Fujitsu Ltd富士通株式会社
    • ISHIZAKA TAEKOWATANABE TAKAYUKI
    • G01M7/08
    • PROBLEM TO BE SOLVED: To solve a problem wherein dropping impact body force is difficult to be measured quantitatively, because impacts are applied a plurality of times onto a tested body, with rebounding after dropping collision, and because results vary greatly according to manners of the collision.
      SOLUTION: This collision testing device is provide with an collision face, a carriage for holding the tested body and moving horizontally, and a cord dropped vertically by a weight connected to an opposite side of the carriage after connected to the carriage via a pulley, and the tested body is prevented from colliding with the collision face the plurality of times, by run-out of the weight out of the cord, when the tested body collides with the collision face.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题为了解决难以定量测量冲击体力的下降的问题,由于冲击多次施加到被测体上,碰撞后具有回弹,并且因为结果根据 碰撞的方式。

      解决方案:该碰撞测试装置提供碰撞面,用于保持被测体并且水平移动的滑架,以及通过连接到滑架的重物经由 滑轮,并且当被测体与碰撞面碰撞时,防止被测体与碰撞面多次碰撞,由重量脱离绳索。 版权所有(C)2007,JPO&INPIT

    • 6. 发明专利
    • SURFACE MOUNT TERMINAL
    • JPH06111869A
    • 1994-04-22
    • JP25873992
    • 1992-09-29
    • FUJITSU LTD
    • ISHIZAKA TAEKO
    • H01R11/01H05K1/14H05K1/18H05K3/34H05K3/36H01R9/09
    • PURPOSE:To facilitate high density mounting and mounting work for a mother printed board by performing surface mount on a bottom surface at the desired position by reflow soldering without being protruding out from the side edge of a module circuit board. CONSTITUTION:This terminal is constituted of narrow conductor substances 22 parallelly provided at an equal pitch from the upper surface to the bottom surface through the side surface of a strip-like insulator 21. The plane part in the upper part of the conductor substance 22 is mounted on a pad 6 parallelly provided in the bottom surface of a module circuit board 5 by reflow soldering. Also, the plane part in the lower part of the conductor substance 22 is mounted on a pad 2 parallelly provided in the surface of a mother printed board 1 by reflow soldering. Thereby, when the surface mounting of other mounting parts 7 is performed on the module circuit print board 5 and also when the surface mount of a module 50 is performed on the mother printed board 1, the reflow soldering for this terminal can be simultaneously performed, so that the simplification and the high efficiency of the work can be achieved. Also, since the surface mount is performed without protruding out from the side edge of the module circuit board 5, the high density mounting of the mother printed board 1 can be achieved.
    • 7. 发明专利
    • DELAY ELEMENT AND IT MANUFACTURE
    • JPH0237814A
    • 1990-02-07
    • JP18692888
    • 1988-07-28
    • FUJITSU LTD
    • ISHIZAKA TAEKOKASAI YOSHIHIKOOKAMURA HAJIME
    • H01P9/00H01P11/00H03H7/34
    • PURPOSE:To attain miniaturization by facing ground patterns in the direction of exposing the ground pattern of a corner part opposite to the one whose base is excised, pasting them, connecting and fixing a ground terminal to the ground pattern of the part exposed in the excised part. CONSTITUTION:A first substrate 21 has a zigzag delay line pattern 26 on a surface 25 of a ceramic substrate main body 23 having a form that the right- lower corner part is excised like a circular arc (24 shows the excised part) from the rectangle of a length L3 and a width W3, and has a ground pattern 28 on the almost whole surface of a rear face 27. A second substrate 22 has the same structure as the first substrate 21, the second substrate is turned at 180 deg. and the rear faces 27 and 27a are pasted oppositely. Ground terminals 35 and 35a are connected and fixed to the parts of the ground patterns 28 and 28a. Thus, the connecting and fixing places of the ground terminals can be ensured, the length of the delay line patterns can be lengthened and the miniaturization can be attained.
    • 8. 发明专利
    • Fixture for drop test
    • 跌倒试验
    • JP2006170641A
    • 2006-06-29
    • JP2004359608
    • 2004-12-13
    • Fujitsu Ltd富士通株式会社
    • WATANABE TAKAYUKIISHIZAKA TAEKO
    • G01N3/303
    • PROBLEM TO BE SOLVED: To provide a fixture for a drop test, used for the drop test for allowing a test target to collide with a collision surface to test the impact resistance of the test target, which has a low cost and reduces the irregularity of the result of the drop test.
      SOLUTION: The fixture for the drop test is constituted of a spherical sheathing body 101 having an electronic component (test target) 105 provided therein and covering the electronic component 105 and the weight 107 attached to the inside of the spherical sheathing body 101. A holder 103, to which the electronic component (test target) 105 and the weight 107 are attached, is attached to the inner wall surface of the spherical sheathing body 101.
      COPYRIGHT: (C)2006,JPO&NCIPI
    • 要解决的问题:为了提供用于跌落试验的夹具,用于允许试验目标与碰撞面碰撞以测试试验对象的耐冲击性,其成本低并且降低 跌落测试结果的不规则性。 解决方案:用于跌落试验的夹具由具有设置在其中的电子部件(试验对象)105的球形护套体101构成,覆盖电子部件105和安装在球状护套体101内部的重物107 安装有电子部件(试验对象物)105和重物107的支架103被安装在球状护套体101的内壁面上。(C)2006年,JPO&NCIPI
    • 9. 发明专利
    • METHOD FOR TESTING DELAY EQUALIZING CIRCUIT
    • JPS59221111A
    • 1984-12-12
    • JP9622283
    • 1983-05-31
    • FUJITSU LTD
    • ISHIZAKA TAEKOOKAMURA HAJIMEKITOU AKIHITO
    • H03H7/01
    • PURPOSE:To exclude a measuring terminal for disconnecting both a series and a parallel resonance circuit from the equalizing circuit by tuning the series resonance circuit to a prescribed frequency and changing the LC of the parallel resonance circuit so as to match the impedance of the input/output of a delay circuit. CONSTITUTION:The series resonance circuit is tuned to a turning frequency f01 by short-circuiting terminals 1,2 at first and adjusting an inductance L2 or a capacitor C2. Then terminals 2,6 are terminated by the characteristic impedance R0 of this circuit, an impedance mismatching attenuation measuring device 12 and a standard resistor Rs(=R0) are connected, and the maximum value (best value) of an impedance mismatching attenuation =(Zin-R0)/(Zin+R0) viewed from the terminals 1,5 is obtained by using them and adjusting the capacitor C2 and the inductance L2 at the tuning frequency f01. Thus this circuit allows to have the characteristic of the full band-pass circuit and the adjusting test of the 2nd order bridged T type delay equalizing circuit is attained.
    • 10. 发明专利
    • ACTIVE FILTER OF TWIN T TYPE
    • JPS5673918A
    • 1981-06-19
    • JP15027079
    • 1979-11-20
    • FUJITSU LTD
    • KANEKO KAZUHIROMATSUZAKI SHINPEIISHIZAKA TAEKO
    • H03H11/12
    • PURPOSE:To make unnecessary the connection of a capacitor to an input of amplifier and to make easy circuit integration, by making variable the gain through an active filter of twin T type having the 1st T circuit consisting of a resistor R, capacitors in CRC arrangement and the 2nd T circuit in RCR arrangement. CONSTITUTION:The 1st T circuit consisting of a resistor R, capacitors C in CRC arrangement has capacitors C1, C2 connected in series, and a resistor R3 which is connected to the connection point of the capacitors as a feedback path from the output of amplifier. Further, the 2nd T circuit in RCR arrangement has resistors R1, R2 and a capacitor C3 which is connected to the connection points between the resistors as a feedback path from the amplifier. The 1st and 2nd T circuits are connected in parallel and to the input terminal of the amplifier A and grounded via a resistor R4. Further, the gain of amplifier is constituted variable with resistors RB, RA and the noncapacitive circuit elements are used for the amplifier as passive elements.