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    • 1. 发明专利
    • TRANSMISSION OUTPUT AUTOMATIC CONTROL SYSTEM
    • JPH0758568A
    • 1995-03-03
    • JP20352793
    • 1993-08-18
    • FUJITSU LTD
    • ISHIGURO HIRONOBU
    • H03F1/30H03G5/16H04L27/20
    • PURPOSE:To realize the transmission output automatic control circuit compensating transmission power fluctuation automatically due to a change in an ambient temperature, a transmission frequency and a power supply voltage. CONSTITUTION:A transmission carrier 100 is modulated at a modulation circuit 1 by input base band signals 101, 102 and its output 103 is controlled at variable attenuators 2, 3, 4 by external control signals 104, CONT2 and SEL1. Part of an output 107 of a power amplifier 5 of a succeeding stage is branched by a coupler 6 and used to provide an attenuation based on the external control signals SEL2, CONT2 through variable attenuators 8, 9, its output 110 is detected by a detector 10 and an envelope is integrated succeedingly by a low pass filter 11 and its output 112 is compared with a reference DC voltage 114 at a comparator 13. A control signal 104 controls the variable attenuator 2. The direction of a change in the attenuation by the variable attenuators 3, 4 and 8, 9 provide the effect opposite to each other and a change in an ambient temperature, a transmission frequency and a power supply voltage is automatically controlled to each circuit.
    • 2. 发明专利
    • VARIABLE FREQUENCY DIVIDER
    • JPS63292824A
    • 1988-11-30
    • JP12908187
    • 1987-05-26
    • FUJITSU LTD
    • SAITO TAMIOSHIGAKI MASAFUMIISHIGURO HIRONOBU
    • H03K23/64H03K23/66
    • PURPOSE:To operate a variable frequency divider at high speed and to miniaturize it as a whole, by frequency-mixing an input signal and a feedback signal, and switching a frequency division output signal which becomes the feedback signal. CONSTITUTION:The output of a frequency divider by three or two FFs provided in a fast variable frequency divider 200 is selected by a change-over switch part 241, and is fed back to a mixer 271. The frequency division coefficient M of the variable frequency divider is decided in two modes corresponding to the selection of the logical state of a mode control signal 207, and an input frequency f0 is frequency-divided. In such a way, the number of the FFs forming the variable frequency divider relatively can be reduced, and the scale of a circuit can be miniaturized. In other words, both features the high speed property of the fast variable frequency divider 200 and the miniaturization of a static type variable frequency divider 300 can be utilized.
    • 4. 发明专利
    • APC CONTROL CIRCUIT FOR TRANSMITTER
    • JPH04361430A
    • 1992-12-15
    • JP13730991
    • 1991-06-10
    • FUJITSU LTD
    • ISHIGURO HIRONOBU
    • H04B1/04
    • PURPOSE:To realize the small sized control circuit with ease of circuit integration in which each APC offset voltage is independently fine-adjusted and an output power is stepwise selected through a DC voltage by an external control data with respect to the APC control circuit for a transmitter keeping the output power stepwise to be a constant output. CONSTITUTION:The control circuit is provided with a conventional high frequency power amplifier 1, detector 2, reference voltage generator 3, differential amplifier 4, multiplexer 5 outputting an APC offset voltage selecting an output level of a high frequency power amplifier in 2 stages, and in addition, with a selector 10 selecting an n-bit data used in common for offset setting of an external input and output control, a decoder 6, a serial/parallel conversion circuit 7 with respect to a serial data for 2 -bit offset, a variable resistor setting circuit 8 applying D/A-conversion to 2 parallel offset setting data being an output of the circuit 7 by using 2 sets of signals being an output of the decoder 6, and outputting the setting data to set the resistance of the 2 sets of the variable resistors, and an electronic volume 9 generating prescribed 2 sets of offset voltages from a DC power supply of a prescribed voltage by the 2 sets of variable resistors.
    • 5. 发明专利
    • DC VOLTAGE GENERATING CIRCUIT
    • JPH04119014A
    • 1992-04-20
    • JP23865190
    • 1990-09-07
    • FUJITSU LTD
    • ISHIGURO HIRONOBU
    • H04B1/04
    • PURPOSE:To facilitate high circuit integration of an APC circuit by decreasing the number of AND gates of a decoder circuit considerably generating a control signal for a switch to select one of DC voltages whose amplitude is gradually and sequentially smaller for an APC circuit. CONSTITUTION:Each of eight DC voltages (DCin8>DCin7...DCin2>DCin1) whose amplitude is smaller sequentially is applied to each input terminal (i) of TAS 8-TAS1 of eight transistor analog switches 308-301. For example, when a 3rd DC voltage DCin3 is selected, since a 3-bit binary signal (codes C, B, A) inputted from a control section 100 is 010, a decoder 200 outputs a code B whose level is '1' in the signal 010 as it is to give a control signal cont3 to the TAS3 of the switch 303. Then high order switches TAS4-TAS8 higher than the switch TAS3 and a least significant switch TAS1 are turned off. Since the function of the decoder 200 is fulfilled by one 3-input AND gate 201, three 2-input AND gates 202-204 and three inverters 206, 207, 208 only, the circuit of the decoder 200 is remarakbly simplified.
    • 6. 发明专利
    • RADIO TRANSMITTER
    • JPH0951280A
    • 1997-02-18
    • JP20308095
    • 1995-08-09
    • FUJITSU LTD
    • ISHIGURO HIRONOBU
    • H04B7/005H04B1/04
    • PROBLEM TO BE SOLVED: To make transmission power constant by widening a transmission band width of a variable low pass filter while a burst signal denoting a rising timing of a slot is applied so as to make the band width narrow while not being applied. SOLUTION: An RC type low pass filter using an analog switch is adopted for a variable low pass filter 51. When a burst signal representing a rising point of time of each slot is applied to a gate of a FETQ1 turned on/off in the variable low pass filter from a control section and the burst signal is at an H level, the FETQ1 is turned off and a time constant is C1.R2. On the other hand, when the burst signal is at an L level, the FETQ1 is turned on, resistors R1, R2 are connected in parallel and the time constant is smaller than the case with only the R1. Since the loop band width is extended in the vicinity of the rising of the time slot, power of an output signal rises up to a specified power within a guard time for burst transient response, and the time constant is increased after the lapse of the guard time and the specified power is maintained.
    • 7. 发明专利
    • MOBILE COMMUNICATION SYSTEM
    • JPH07264651A
    • 1995-10-13
    • JP4960194
    • 1994-03-18
    • FUJITSU LTD
    • ISHIGURO HIRONOBUSHIBATA MANABU
    • H04B7/26H04W16/26H04W48/20H04W56/00H04W76/00H04W92/00H04Q7/22H04Q7/28H04Q7/36
    • PURPOSE:To provide the low-cost, high-performance mobile communication system which is suitable for communication service in the beginning of system introduction or in an area wherein there are a small number of subscribers, etc. CONSTITUTION:This system is equipped with peripheral base stations SBS which are decentralized and arranged in respective peripheral zones formed by dividing a specific area, receive sent waves from mobile machines MS, and convert them to respective specific different frequencies and resend them, and a master base station MSB which is connected to a mobile object exchange MCS, arranged in a zone surrounded with the peripheral zones, and put in charge of mobile communication service in the specific area. The master base station MSB sends sent data from the mobile object exchange MCS with an output level covering the specific area when sending them as an outgoing radio wave to the mobile machine MS, and receive incoming direct waves from the mobile machines MS and incoming radio waves resent through plural peripheral base stations SBS at the same time when receiving the incoming radio waves from the mobile machines MS, thereby selecting the received data of the path in the best reception state. Each peripheral base station SBS preferably has the same amplification gain.
    • 8. 发明专利
    • HIGH FREQUENCY POWER AMPLIFIER PROTECTION CIRCUIT
    • JPH0358507A
    • 1991-03-13
    • JP19464489
    • 1989-07-26
    • FUJITSU LTD
    • ISHIGURO HIRONOBU
    • H02H5/04H03F1/52
    • PURPOSE:To attain continuous communication while protecting a high frequency power amplifier from burning due to heat by providing a logic output section sending a control signal decreasing transmission power to the high frequency power amplifier so as to reduce the transmission power. CONSTITUTION:A transmission part 1 is provided with a temperature sensor 12 sensing a temperature of a high frequency power amplifier 11, a comparator circuit 22 of a logic control section 2 compares a temperature data set by a temperature setting circuit 21 with the detected temperature data and gives an output when the detected temperature data exceeds the set temperature data and a logic output section 23 outputs a control signal to the high frequency power amplifier 11 by the output of the comparator circuit 22. Then the transmission power of the high frequency power amplifier 11 is reduced to prevent burning of the high frequency power amplifier 11. Thus, disabled communication due to interruption of power supply is avoided and continuous communication is attained while protecting the high frequency power amplifier 11.
    • 9. 发明专利
    • DIFFERENTIAL AMPLIFIER
    • JPS63227205A
    • 1988-09-21
    • JP6216987
    • 1987-03-17
    • FUJITSU LTD
    • SAITO TAMIOSHIGAKI MASAFUMIISHIGURO HIRONOBU
    • H03F3/45
    • PURPOSE:To improve a frequency characteristic, by generating peaking by inserting inductances between the output side of a differential pair of FETs and the input side of the FET of a buffer circuit, respectively. CONSTITUTION:The FETs 11 and 22 are operated as the differential pair of amplifiers, and generate outputs respectively, and respective output is connected to an external circuit via the FETs 13 and 14 which constitute the buffer circuit. At this time, by inserting the inductances 51 and 52 between the output side of the FETs 11 and 12, and the input sides of the FFTs 13 and 14 respectively, resonance is generated by a capacitor on the output side of the FETs 11 and 12, the inductances 51 and 52, and the capacitor on the input side of the FETs 13 and 14, and the peaking is generated at the high-pass area of the frequency characteristic, then, a gain at the part can be increased. In such a way, it is possible to improve the frequency characteristic compared with a case that no inductances 51 and 52 are used.