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1. 发明专利

JPH1152030A METHOD AND DEVICE FPR CREATING TEST PATTERN FOR LOGIC CIRCUIT AND TEST METHOD AND DEVICE FOR LOGIC CIRCUIT 失效
公开(公告)号：JPH1152030A
公开(公告)日：1999-02-26
申请号：JP21504697
申请日：1997-08-08
申请人： FUJITSU LTD
发明人： KONISHI HIDEAKI , ETO TAKESHI
IPC分类号： G01R31/28 , G01R31/3183
摘要： PROBLEM TO BE SOLVED: To obtain test patterns efficient in detecting faults by estimating the probability of occurrence of faults to be sampled in logic circuits according to the layout of the logic circuits, arranging faults in order of decreasing probability on the basis of the obtained probability of detected faults, and creating test patterns obtained by compressing patterns in which faults overlap. SOLUTION: A test pattern creating device 2 executes program for test patterns stored in advance in program memory 12 by a processing part 13 in response to instructions from an input device 17 and creates test patterns on the basis of the layout information of logic integrated circuits 3-1 to 3-n to be tested stored in advance in a layout information storage part 11. In fault information, a higher priority is assigned to a fault which easily occurs, and a fault with a higher priority is compressed into a pattern so that it can be priorly processed. A testing device 4 detects output patterns from the logic circuits 3-1 to 3-n and determines whether they are logically normal or not. In the case that they are not logically normal i.e., the logic circuits are faulty, later tests are canceled to indicate the presence of a fault.

2. 发明专利

JP2000259699A SYNTHESIZER FOR LOGICAL CIRCUIT AND RECORDING MEDIUM 失效
公开(公告)号：JP2000259699A
公开(公告)日：2000-09-22
申请号：JP6418899
申请日：1999-03-11
申请人： FUJITSU LTD
发明人： ETO TAKESHI
IPC分类号： H03K19/00 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To simplify the constitution of a circuit by executing automatic synthesis by using the multiplication or division of a succeeding step as a shifter when a change in a signal outputted from a preceding step is a power of 2 on the description of circuit operation in respect of a synthesizer for executing logical synthesis on the basis of the description of circuit operation and a recording medium. SOLUTION: The synthesizer is provided with a means for judging whether only a power of 2 is transferred from the preceding step or not on the basis of the description of circuit operation and a means for executing synthesis (S4) by using multiplication or division description of the succeeding step as a shifter at the time of judging that only a power of 2 is transferred from the preceding step, and in other cases, executing synthesis by the multiplication or division description itself (S5).

3. 发明专利

JP2002073345A INFORMATION PROCESSING SYSTEM AND STORAGE MEDIUM 失效
公开(公告)号：JP2002073345A
公开(公告)日：2002-03-12
申请号：JP2000255317
申请日：2000-08-25
申请人： FUJITSU LTD
发明人： ETO TAKESHI
IPC分类号： G06F9/45
摘要： PROBLEM TO BE SOLVED: To execute a program for a virtual machine faster. SOLUTION: The program loader 16 reads out a byte code from the cluster file 12, decides whether a load location of this byte code and an argument setup byte code is the Java virtual machine 13 or the JIT compiler 15 based on content of a determination information storage unit 17 if the byte code is a subroutine call and iterates a loading process for the byte code to the decided load location. If the byte code is not the subroutine call, the loading location is decided to Java virtual machine 13. The content of determination information storage unit 17 is decided by the static analyzer 18 to analyze the content of the cluster file 16 or a person before the cluster file 12 is executed.

4. 发明专利

JPH05242054A 失效
公开(公告)号：JPH05242054A
公开(公告)日：1993-09-21
申请号：JP3981892
申请日：1992-02-26
申请人： FUJITSU LTD
发明人： ETO TAKESHI
IPC分类号： G06F15/16 , G06F15/173
摘要： PURPOSE:To improve and speed up a parallel data processing by introducing both an auxiliary control means and a data compressing means without depending on a main control means, in various data transfer between data processing/controlling elements and a main storage device. CONSTITUTION:This device is a device processing various data D in parallel with plural data processors PE1, PE2, PEi and PEj-PEn and is constituted of a data transfer means 11 which transfers various data D, plural data processors PE1, PE2, PEi and PEj-PEn connected to a control line 12 which transfers control signals and a main control means 13 which monitors the data processors PE1, PE2, PEi and PEj-PEn. Further, a data compressing means 14 which compresses and transfers various data D is included.

5. 发明专利

JP2003271448A Stack management method and information processing device 审中-公开
标题翻译：堆栈管理方法和信息处理设备
公开(公告)号：JP2003271448A
公开(公告)日：2003-09-26
申请号：JP2002074732
申请日：2002-03-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAGANUMA MASAYUKI , ETO TAKESHI
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0223 , G06F2212/451
摘要： PROBLEM TO BE SOLVED: To provide a method for managing a stack storage area, capable of executing a stack extension processing by efficiently using a working area.
SOLUTION: In this stack management method, a temporary stack storage area is beforehand provided in a predetermined storage area. When overflow occurs in a current stack storage area in a main storage space, the temporary stack storage area is assigned in the memory area which continues from the current stack storage area and by using this temporary stack storage area as the working area, a new stack storage area is secured to execute a stack extension processing for the current stack storage area.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种用于管理堆栈存储区域的方法，能够通过有效地使用工作区域来执行堆栈扩展处理。解决方案：在该堆叠管理方法中，预先在预定的存储区域中提供临时堆栈存储区域。当在主存储空间中的当前堆栈存储区域发生溢出时，临时堆栈存储区域被分配在从当前堆栈存储区域继续的存储区域中，并且通过使用该临时堆栈存储区域作为工作区域，存储区域被确保以对当前堆栈存储区域执行堆栈扩展处理。版权所有（C）2003，JPO

6. 发明专利

JP2002268897A THREAD MANAGING METHOD AND INFORMATION PROCESSOR 失效
公开(公告)号：JP2002268897A
公开(公告)日：2002-09-20
申请号：JP2001064415
申请日：2001-03-08
申请人： FUJITSU LTD
发明人： AOKI TAKASHI , ETO TAKESHI
IPC分类号： G06F12/08 , G06F9/46
摘要： PROBLEM TO BE SOLVED: To perform efficient management by removing an over-head in memory reference in program thread management. SOLUTION: A thread managing method and an information processor are for realizing a multi-thread processing in a virtual machine. The processor is provided with a processing means 1a for processing information, a memory 2 for storing information and a cache area 3a to which access is performed at high speed. The processing means 1a puts thread management information for managing a thread being performed at present into the cache area from the memory.

7. 发明专利

JPH1196197A LOGICAL SYNTHESIS METHOD 失效
公开(公告)号：JPH1196197A
公开(公告)日：1999-04-09
申请号：JP25255697
申请日：1997-09-18
申请人： FUJITSU LTD
发明人： ETO TAKESHI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To execute an efficient logical synthesis by simples operation description in a logical synthesis method for executing logical synthesis from the operation description of a logical circuit. SOLUTION: When branch conditions 2'b01, 2'b10 other than previously described branch conditions 2'b00, 2'b11 are not generated in operation description 7, in which whether a selector is to be generated or a latch circuit is to be generated is not clear as the result of logical simulation for the operation description of a logical circuit, a selector 8 is generated. A message output instruction is added to the description 7 as default operation, and when branch the conditions 2'b01, 2'b10 other than the previously described branch conditions 2'b00, 2'b11 are generated, a latch circuit 9 is generated.

8. 发明专利

JPH08114656A TEST PATTERN FORMING METHOD FOR LOGIC INTEGRATED CIRCUIT AND TESTING METHOD USING THE SAME 失效
公开(公告)号：JPH08114656A
公开(公告)日：1996-05-07
申请号：JP25033194
申请日：1994-10-17
申请人： FUJITSU LTD
发明人： TAKEYAMA KOJI , ETO TAKESHI
IPC分类号： G01R31/3183
摘要： PURPOSE: To form a test pattern having an excellent testing efficiency without waiting the formation of a logic integrated circuit and to test by using it. CONSTITUTION: A test, in which input patterns are sequentially supplied to a logic integrated circuit and whether the output pattern taken out from the circuit coincides with an expected value pattern or not is judged, is conducted. When mismatch is judged, the testing of the circuit is stopped, and the circuit of next equal type is tested. Before the circuit is formed, the fault occurrence degree of the disconnection or the short-circuit of a signal line is estimated according to wiring conditions obtained from wiring design data, the lines are aligned in the order of estimated fault occurrence degrees, a test pattern for detecting the fault of the line is formed, and used in the descending order of the degree. The estimated fault occurrence degree is so decided that the more the times of crossing a power source supply line is, the longer the wiring length is, the more the number of times of replacing a wiring layer, and the higher the wiring density is, the higher the degree becomes.

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