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JP2011252802A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011252802A
公开(公告)日：2011-12-15
申请号：JP2010126945
申请日：2010-06-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： OKUMOTO MASASHI , MOCHIDA YOSHIFUMI
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for initializing using a test mode the output of a level adjustment circuit erroneously set up when the power supply is turned on, and adjusting the output of the level adjustment circuit at a high speed to a regular setting value that is a target level.SOLUTION: The semiconductor device comprises: a plurality of latch circuits 2 for holding test data inputted from the outside in a test mode; a decode circuit 3 for inputting the test data held by the latch circuits 2 to generate a code by a combination of logic of the test data; a transition detection circuit 7 for outputting gate drive signals UPDN_B , UPDN_T , and UPDN_T which are at an H level or an L level during a preset period when the logic level of the test data held by the latch circuits 2 changes to drive a current supply circuit (a reducing circuit 8, a raising circuit 9).
摘要翻译：要解决的问题：为了提供使用测试模式初始化的半导体器件，当电源接通时错误地设置的电平调节电路的输出，并且调整以高速作为目标水平的常规设定值。解决方案：半导体器件包括：多个锁存电路2，用于在测试模式下保持从外部输入的测试数据; 解码电路3，用于输入由锁存电路2保持的测试数据，以通过测试数据的逻辑的组合生成代码; 一个转换检测电路7，用于在预设时段期间输出作为H电平或L电平的门电路驱动信号UPDN_B，UPDN_T，和UPDN_T

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