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1. 发明专利

JP2010141107A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010141107A
公开(公告)日：2010-06-24
申请号：JP2008315679
申请日：2008-12-11
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L21/8242 , H01L21/76 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/108 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same for maintaining lower contact resistance between a contact plug and a diffusing layer even under the condition that an area between the adjacent active regions becomes narrow.
SOLUTION: The semiconductor device has: gate trenches 103gt
1 , 103gt
2 , and a dummy gate trench 103dgt provided in an active region 102 extended in the X direction; and gate electrodes 104g
1 , 104g
2 and a dummy gate 104dg which are extended in the Y direction crossing the active region 102 and respectively embedded at least in a part thereof within the trenches 103gt
1 , 103gt
2 , 103dgt. A transistor 109 formed of the gate electrode 104g
1 and diffusing layers 105a
1 , 105a
2 provided in both sides of this gate electrode 104g
1 and a transistor 110 formed of the gate electrode 104g
2 and diffusing layers 105b
1 , 105b
2 provided in both sides of this gate electrode 104g
2 are separated for insulation by the dummy gate 104dg arranged between the diffusing layers 105a
2 and 105b
1 .
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：即使在相邻的活性区域之间的区域变窄的条件下，提供一种用于保持接触插塞和漫射层之间较低接触电阻的半导体器件及其制造方法。解决方案：半导体器件具有：设置在沿X方向延伸的有源区域102中的栅极沟槽103gt <1>，103gt 2 和伪栅极沟道103dgt; 以及在Y方向上与激活区域102交叉并分别嵌入其中的至少一部分的栅电极104g <1>，104g＆lt; SB＆gt;和伪栅极104dg。沟槽103gt <1>，103gt 2 ，103dgt。由栅电极104g 和设置在该栅电极的两侧的扩散层105a ，105a 2 形成的晶体管109 2 被分隔开，通过布置在漫射层105a和第二区域12之间的伪栅极104dg绝缘。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009070975A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009070975A
公开(公告)日：2009-04-02
申请号：JP2007236790
申请日：2007-09-12
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L29/78 , H01L21/76
CPC分类号： H01L29/66621
摘要： PROBLEM TO BE SOLVED: To attain embedding performance and reduction in channel resistance for an inter-diffusion-layer isolation insulating film in a semiconductor device of a trench gate structure having diffusion layers and an inter-diffusion-layer isolation insulating film partly recessed, formed in a semiconductor substrate.
SOLUTION: In the trench forming a trench gate structure, an inter-diffusion-layer isolation insulating film is selectively wet etched to a diffusion layer so that the diffusion layer is projected, and the projected diffusion layer is selectively epitaxially grown so that the projected portion of the diffusion layer forms an eaves structure.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题为了在具有扩散层和扩散层隔离绝缘膜的沟槽栅极结构的半导体器件中获得嵌入性能和沟道电阻降低部分扩散层隔离绝缘膜的沟道电阻凹陷，形成在半导体衬底中。解决方案：在形成沟槽栅极结构的沟槽中，将扩散层隔离绝缘膜选择性地湿式蚀刻到扩散层，使得扩散层被投射，并且投影的扩散层被选择性地外延生长，使得扩散层的突出部分形成屋檐结构。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2007005502A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2007005502A
公开(公告)日：2007-01-11
申请号：JP2005182693
申请日：2005-06-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： HASUNUMA EIJI , KAWAKITA KEIZO , TANAKA YOSHINORI , MIKASA NORIAKI
IPC分类号： H01L21/8242 , G11C11/401 , H01L27/108
CPC分类号： G11C7/18 , G11C11/4097
摘要： PROBLEM TO BE SOLVED: To reduce an area of an end memory cell mat in a DRAM device.
SOLUTION: A memory cell of the end memory cell mat 20 dares to be of a type of larger area than the memory cell of a general memory cell mat 10, and an advantage of a folded bit line structure can be carried into an open bit line structure. Thus, the end memory cell mat 20 can be reduced in size as a whole. For instance, the memory cell of the general memory cell mat 10 is formed as a 6F
2 cell, whereas the memory cell of the end memory cell mat 20 is formed as an 8F
2 cell.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：减少DRAM装置中的端部存储单元垫的面积。解决方案：结束存储单元阵列20的存储单元可能是与通用存储单元阵列10的存储单元相比更大的面积的类型，并且折叠的位线结构的优点可以被传送到打开位线结构。因此，结束存储单元垫20的整体尺寸可以减小。例如，一般存储单元阵列10的存储单元形成为6F 2 单元，而最终存储单元阵列20的存储单元形成为8F 2 < SP>细胞。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2012248686A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012248686A
公开(公告)日：2012-12-13
申请号：JP2011119360
申请日：2011-05-27
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L21/8242 , H01L21/336 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10855
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing channel resistance and increasing ON-state current, and making each transistor operate independently and stably, and provide a manufacturing method of the same.SOLUTION: A semiconductor device comprises a first impurity diffusion region 27 provided at a bottom of a gate electrode trench 18, a second impurity diffusion region 28 provided on a semiconductor substrate 13 so as to cover an upper part 21A of a gate insulation film 21 arranged on a first lateral face 18a, and a third impurity diffusion region 29 provided on the semiconductor substrate 13 so as to cover the gate insulation film 21 arranged at least on a second lateral face 18b and joined with the first impurity diffusion region 27.
摘要翻译：要解决的问题：提供能够降低通道电阻和增加导通电流的半导体器件，并且使每个晶体管独立且稳定地工作，并提供其制造方法。解决方案：半导体器件包括设置在栅极电极沟槽18的底部的第一杂质扩散区域27，设置在半导体衬底13上的第二杂质扩散区域28，以覆盖栅绝缘体的上部21A 布置在第一侧面18a上的膜21和设置在半导体衬底13上的第三杂质扩散区29，以覆盖至少布置在第二侧面18b上并与第一杂质扩散区27连接的栅极绝缘膜21 。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2012174790A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012174790A
公开(公告)日：2012-09-10
申请号：JP2011033431
申请日：2011-02-18
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10888
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which achieve increase in a contact area between an active region and a bit line contact, and reduction of contact resistance.SOLUTION: A semiconductor device 100 according to the present invention comprises: first trenches 4 formed on a substrate 1 and extending in a first direction; second insulation layers 6 each formed by embedding of a lower part of the first trench 4; a plurality of second trenches formed on the substrate 1 and extending in a second direction orthogonal to the first direction; word lines each formed in the second trench by embedding of a lower part of the second trench; semiconductor pillars 1d formed in the substrate 1 in regions sectioned by the first trenches 4 and the second trenches to be vertically arranged in the substrate 1 and each having a diffusion region 23a on an upper part; bit line contacts 22a respectively connected with the semiconductor pillars 1d aligned in the first direction for every predetermined number of semiconductor pillars, each bit line contact being connected on the diffusion region 23a via a lateral face of the upper part; and bit lines 26 connected with the bit line contacts 22a, respectively.
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，其实现有源区和位线接触之间的接触面积的增加以及接触电阻的降低。解决方案：根据本发明的半导体器件100包括：形成在基板1上并沿第一方向延伸的第一沟槽4; 每个通过嵌入第一沟槽4的下部形成的第二绝缘层6; 多个第二沟槽，形成在基板1上并沿与第一方向正交的第二方向延伸; 通过嵌入第二沟槽的下部而在第二沟槽中形成的字线; 在由第一沟槽4和第二沟槽分割的区域中形成在基板1中的半导体柱1d被垂直布置在基板1中，并且在上部具有扩散区域23a; 分别与每个预定数量的半导体柱对准在第一方向上的半导体柱1d连接的位线触点22a，每个位线触点经由上部的侧面连接在扩散区23a上; 以及分别与位线接点22a连接的位线26。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2011014750A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011014750A
公开(公告)日：2011-01-20
申请号：JP2009158345
申请日：2009-07-03
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L29/78 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/66628 , H01L21/3083 , H01L21/76229 , H01L29/1037 , H01L29/4236 , H01L29/66621 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent a partial concentration of electric field in an active region.SOLUTION: A semiconductor device is equipped with a first diffusion region and a second diffusion region that are formed in an active region surrounded by an isolation insulating region (6); a groove-shaped trench region formed between the first diffusion region and the second diffusion region; a gate insulating film (10) formed on the trench region; a gate electrode (11) so formed on the gate insulating film as to let the trench region be embedded in the gate electrode; and a protective insulating film (4), formed in a region located on the upper layer side of a region sandwiched between the gate insulating film and the isolation insulating region.
摘要翻译：要解决的问题：为了防止有源区域中的电场的局部浓缩。解决方案：半导体器件配备有形成在由隔离绝缘区域（6）包围的有源区域中的第一扩散区域和第二扩散区域）; 形成在所述第一扩散区域和所述第二扩散区域之间的沟槽状沟槽区域; 形成在所述沟槽区域上的栅极绝缘膜（10）形成在所述栅极绝缘膜上以使所述沟槽区域嵌入所述栅电极的栅电极（11）; 以及保护绝缘膜（4），形成在位于所述栅极绝缘膜和所述隔离绝缘区域之间的区域的上层侧的区域中。

7. 发明专利

JP2010021328A Semiconductor device and manufacturing method thereof, and data processing system 审中-公开
标题翻译：半导体器件及其制造方法及数据处理系统
公开(公告)号：JP2010021328A
公开(公告)日：2010-01-28
申请号：JP2008179979
申请日：2008-07-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
CPC分类号： H01L29/4236 , H01L21/823456 , H01L29/0653 , H01L29/66621
摘要： PROBLEM TO BE SOLVED: To fabricate recess-channel transistors having different characteristics simultaneously in the same step. SOLUTION: A method of manufacturing a semiconductor device includes a step wherein a semiconductor substrate 2 is etched using hard masks 71-73 and sidewall insulation films 38 are formed on the side faces of the hard masks 71-73, and then the sidewall insulation films 38 formed on the side faces of the hard masks 71 and 72 are selectively removed, and thereafter the semiconductor substrate 2 is further etched using the hard masks 71-73 and the sidewall insulation film 38 to form gate trenches 12, 22, 32 simultaneously in a portion of the semiconductor substrate 2 which has been covered by the hard masks 71-73; and a step of forming gate electrodes 13, 23, 33 inside the gate trenches 12, 22, 32. Thereby, multiple recess-channel transistors with different heights for fin-like regions 21f and 31f can be fabricated simultaneously. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在同一步骤中同时制造具有不同特性的凹槽通道晶体管。解决方案：制造半导体器件的方法包括其中使用硬掩模71-73蚀刻半导体衬底2并且在硬掩模71-73的侧面上形成侧壁绝缘膜38的步骤，然后将选择性地去除在硬掩模71和72的侧面上形成的侧壁绝缘膜38，然后使用硬掩模71-73和侧壁绝缘膜38进一步蚀刻半导体基板2，以形成栅极沟槽12,22， 32同时在半导体衬底2的被硬掩模71-73覆盖的部分中; 以及在栅极沟槽12,22,32内形成栅电极13,23,33的步骤。由此，可以同时制造用于鳍状区域21f和31f的具有不同高度的多个凹槽沟道晶体管。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2010016220A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010016220A
公开(公告)日：2010-01-21
申请号：JP2008175519
申请日：2008-07-04
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L21/8242 , H01L21/768 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/10855
摘要： PROBLEM TO BE SOLVED: To prevent contact between a bit contact and a capacitance contact.
SOLUTION: A semiconductor device includes: a transistor 111 having diffusion layer regions 121, 122; cell contacts 131, 141 embedded in an interlayer insulating film 151, and connected to the diffusion layer regions 121, 122, respectively; a bit contact 132 embedded in an interlayer insulating film 152, and connected to the cell contact 131; a bit wire 130 embedded in an interlayer insulating film 153, and connected to the bit contact; and a capacitance contact 142 embedded in the interlayer insulating films 152, 153, and connected to the cell contact 141, wherein a side surface 130a of the bit wire 130 coincides with side surface 132a of the bit contact 132 along an extending direction of the bit wire 130. Consequently, the bit contact is not directly short-circuited to the capacitance contact, thereby enlarging the formation margin of the capacitance contact.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：防止位触点和电容触点之间的接触。解决方案：半导体器件包括：具有扩散层区域121,122的晶体管111; 嵌入在层间绝缘膜151中的单元触点131,141分别连接到扩散层区域121,122; 嵌入在层间绝缘膜152中的位触点132，并连接到电池触点131; 位于层间绝缘膜153中的位线130，并与该位触点相连接; 以及嵌入在层间绝缘膜152,153中并连接到电池触点141的电容触点142，其中位线130的侧表面130a与钻头触头132的侧表面132a沿钻头的延伸方向重合因此，位触点不直接与电容触点短路，从而扩大了电容触点的形成边缘。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2008171872A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008171872A
公开(公告)日：2008-07-24
申请号：JP2007001335
申请日：2007-01-09
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L29/7851 , H01L29/66621 , H01L29/66795
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a three-dimensionally structured gate insulating film which can easily deal with miniaturization of a gate structure and be easily manufactured. SOLUTION: This semiconductor device has a structure in which a three-dimensionally structured gate insulating film is formed on a semiconductor substrate, a gate electrode contacting the gate insulating film is protrudingly formed on the semiconductor substrate, a source electrode and a drain electrode are formed on the semiconductor substrate around the gate insulating film via a diffusion layer region of the semiconductor substrate, the upper surface of the semiconductor substrate around the gate electrode is covered with a protective insulating film for covering the side surface of the gate electrode protrudingly formed on the semiconductor substrate, and an interlayer insulating film is laminated on the protective insulating film. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有三维结构的栅绝缘膜的半导体器件，其可以容易地处理栅极结构的小型化并且容易制造。解决方案：该半导体器件具有在半导体衬底上形成三维结构的栅极绝缘膜的结构，与栅极绝缘膜接触的栅电极突出地形成在半导体衬底上，源电极和漏极电极通过半导体衬底的扩散层区域形成在栅极绝缘膜周围的半导体衬底上，栅电极周围的半导体衬底的上表面被用于覆盖栅电极的侧表面的保护绝缘膜覆盖形成在半导体衬底上，层间绝缘膜层叠在保护绝缘膜上。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2008124098A Semiconductor device, and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008124098A
公开(公告)日：2008-05-29
申请号：JP2006303558
申请日：2006-11-09
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIKASA NORIAKI
IPC分类号： H01L29/78
CPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To achieve high-speed operation of MISFET by reducing a bonding capacitance without lowering an ON-current of MISFET.
SOLUTION: The source/drain regions 16, 17 of MISFET are respectively formed of a selectively grown silicon layer 22 and a plurality of divided diffusion layer regions 21a that are connected integrally with the selectively grown silicon layer 22. The divided diffusion layer regions 21a are mutually isolated with a diffusing layer dividing region 23 formed with the STI method.
COPYRIGHT: (C)2008,JPO&INPIT

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